IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet
IDT82P2284
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IDT82P2284 Summary of contents
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... Quad T1/E1/J1 Long Haul / Short Haul Transceiver IDT82P2284 2975 Stender Way, Santa Clara, Califormia 95054 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Version 3 March 22, 2004 Printed in U.S.A. © 2001 Integrated Device Technology, Inc. ...
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... Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
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FEATURES ........................................................................................................................................................................ 1 APPLICATIONS ................................................................................................................................................................ 1 BLOCK DIAGRAM ............................................................................................................................................................ 2 1 PIN ASSIGNMENT ............................................................................................................................................................ 3 2 PIN DESCRIPTION ........................................................................................................................................................... 4 3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ 12 3 MODE SELECTION .................................................................................................................................................................. 14 3.2 RECEIVER IMPEDANCE MATCHING ......................................................................................................................................................... ...
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... IDT82P2284 3.8.2.3.3 National Bit Extraction ................................................................................................................................... 35 3.8.2.3.4 National Bit Codeword Extraction .................................................................................................................. 35 3.8.2.3.5 Extra Bit Extraction ........................................................................................................................................ 35 3.8.2.3.6 Remote Signaling Multi-Frame Alarm Indication Bit Extraction ..................................................................... 35 3.8.2.3.7 Sa6 Code Detection Per ETS 300 233 .......................................................................................................... 35 3.8.2.4 V5.2 Link .......................................................................................................................................................................... 36 3.8.2.5 Interrupt Summary ............................................................................................................................................................ 36 3.9 PERFORMANCE MONITOR ........................................................................................................................................................................ 38 3.9.1 T1/J1 Mode ...................................................................................................................................................................................... 38 3.9.2 E1 Mode .......................................................................................................................................................................................... 40 3.10 ALARM DETECTOR .................................................................................................................................................................................... 42 3.10.1 T1/J1 Mode ...................................................................................................................................................................................... 42 3.10.2 E1 Mode .......................................................................................................................................................................................... 44 3.11 HDLC RECEIVER ......................................................................................................................................................................................... 45 3.11.1 HDLC Channel Configuration ........................................................................................................................................................ 45 3 ...
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... IDT82P2284 3.18.2.2 Transmit Clock Slave Mode ............................................................................................................................................. 67 3.18.2.3 Transmit Multiplexed Mode .............................................................................................................................................. 68 3.18.2.4 Offset ................................................................................................................................................................................ 68 3.19 TRANSMIT PAYLOAD CONTROL .............................................................................................................................................................. 69 3.20 FRAME GENERATOR ................................................................................................................................................................................. 70 3.20.1 Generation ...................................................................................................................................................................................... 70 3.20.1 Mode .................................................................................................................................................................... 70 3.20.1.1.1 Super Frame (SF) Format ............................................................................................................................. 70 3.20.1.1.2 Extended Super Frame (ESF) Format ........................................................................................................... 70 3.20.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 70 3.20.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 70 3.20.1.1.5 Interrupt Summary ......................................................................................................................................... 71 3.20.1.2 E1 Mode ........................................................................................................................................................................... 72 3.20.1.2.1 Interrupt Summary ......................................................................................................................................... 73 3 ...
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... IDT82P2284 3.27.2.6 Analog Loopback .............................................................................................................................................................. 92 3.27.3 G.772 Non-Intrusive Monitoring .................................................................................................................................................... 92 3.28 INTERRUPT SUMMARY .............................................................................................................................................................................. 95 4 OPERATION .................................................................................................................................................................... 96 4.1 POWER-ON SEQUENCE ............................................................................................................................................................................. 96 4.2 RESET .......................................................................................................................................................................................................... 96 4.3 RECEIVE / TRANSMIT PATH POWER DOWN ........................................................................................................................................... 96 4.4 MICROPROCESSOR INTERFACE ............................................................................................................................................................. 97 4.4.1 SPI Mode ......................................................................................................................................................................................... 97 4.4.2 Parallel Microprocessor Interface ................................................................................................................................................ 98 4.5 INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................. 99 4.5.1 Indirect Register Read Access ..................................................................................................................................................... 99 4.5.2 Indirect Register Write Access ..................................................................................................................................................... 99 5 PROGRAMMING INFORMATION ................................................................................................................................. 100 5 ...
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... IDT82P2284 7.12.1.1 Read Cycle Specification ............................................................................................................................................... 366 7.12.1.2 Write Cycle Specification ................................................................................................................................................ 367 7.12.2 Intel Non-Multiplexed Mode ......................................................................................................................................................... 368 7.12.2.1 Read Cycle Specification ............................................................................................................................................... 368 7.12.2.2 Write Cycle Specification ................................................................................................................................................ 369 7.12.3 SPI Mode ....................................................................................................................................................................................... 370 ORDERING INFORMATION ......................................................................................................................................... 373 Table of Contents QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER v March 22, 2004 ...
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Table 1: Operating Mode Selection ........................................................................................................................................................................... 14 Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 14 Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 15 Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 16 Table ...
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... IDT82P2284 Table 49: Interrupt Summary In E1 Mode .................................................................................................................................................................... 73 Table 50: Related Bit / Register In Chapter 3.20.1.2 ................................................................................................................................................... 74 Table 51: Related Bit / Register In Chapter 3.20.2.1 ................................................................................................................................................... 75 Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4 .................................................................................................................... 76 Table 53: APRM Message Format .............................................................................................................................................................................. 77 Table 54: APRM Interpretation .................................................................................................................................................................................... 77 Table 55: Related Bit / Register In Chapter 3.20.3 ...................................................................................................................................................... 78 Table 56: Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5 .......................................................................................................................... 78 Table 57: Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 & ...
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Figure 1. 208-Pin PBGA (Top View) ............................................................................................................................................................................. 3 Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 15 Figure 3. Monitoring Receive Path .............................................................................................................................................................................. 16 Figure 4. Monitoring Transmit Path ............................................................................................................................................................................. 16 Figure 5. Jitter Attenuator ............................................................................................................................................................................................ 18 Figure 6. AMI ...
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... IDT82P2284 Figure 49. Intel Non-Multiplexed Mode Read Cycle .................................................................................................................................................. 368 Figure 50. Intel Non-Multiplexed Mode Write Cycle .................................................................................................................................................. 369 Figure 51. SPI Timing Diagram ................................................................................................................................................................................. 370 List of Figures QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER ix March 22, 2004 ...
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... Low power consumption (Typical 450 mW) • 3.3 V and 1.8 V power supply • 208-pin PBGA package APPLICATIONS • C.O, PABX, ISDN PRI • Wireless Base Stations • T1/E1/J1 ATM Gateways, Multiplexer • T1/E1/J1 Access Networks • LAN/WAN Router • Digital Cross Connect • SONET/SDH Add/Drop Equipment TM ST- 1 IDT82P2284 March 22, 2004 DSC-6226/3 ...
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... IDT82P2284 BLOCK DIAGRAM Block Diagram QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER 2 REFB_OUT REFA_OUT CLK_SEL[2:0] OSCO OSCI CLK_GEN_1.544 CLK_GEN_2.048 GPIO[1:0] RESET THZ A[9:0] D[7:1] D[0]/SDO CS REFR RW/WR/SDI DS/RD/SCLK MPM SPIEN INT TDO TDI TMS TCK TRST March 22, 2004 ...
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... IDT82P2284 1 PIN ASSIGNMENT TTIP4 TRING4 VDDAT4 VDDAR4 B NC VDDAX4 GNDA RTIP4 GNDA RRING4 GNDA GNDA E TSIG2 MTSIGB1 F TSIG1/ TSD2/ TSD4 TSIG4 MTSIGA1 MTSDB1 G TSD1/ TSFS4 TSD3 TSIG3 MTSDA1 H TSFS3 TSCK4 NC J TSCK3 TSFS2 NC TSFS1/ K TSCK2 NC MTSFS ...
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... IDT82P2284 2 PIN DESCRIPTION Name Type Pin No. RTIP[1] Input RTIP[2] RTIP[3] RTIP[4] RRING[1] RRING[2] RRING[3] RRING[4] TTIP[1] Output TTIP[2] TTIP[3] TTIP[4] TRING[1] TRING[2] TRING[3] TRING[4] RSD[1] / MRSDA[1] High-Z RSD[2] / MRSDB[1] Output RSD[3] RSD[4] RSIG[1] / MRSIGA[1] High-Z RSIG[2] / MRSIGB[1] Output RSIG[3] RSIG[4] Note: * The contents in the brackets indicate the position of the preceding bit and the address of the register. After the address, if the punctuation ‘ ...
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... IDT82P2284 Name Type Pin No. RSFS[1] / MRSFS Output / Input RSFS[2] RSFS[3] RSFS[4] RSCK[1] / MRSCK Output / Input RSCK[2] RSCK[3] RSCK[4] TSD[1] / MTSDA[1] Input TSD[2] / MTSDB[1] TSD[3] TSD[4] Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER N5 RSFS[1:4]: Receive Side System Frame Pulse for Link ...
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... IDT82P2284 Name Type Pin No. TSIG[1] / MTSIGA[1] Input TSIG[2] / MTSIGB[1] TSIG[3] TSIG[4] TSFS[1] / MTSFS Output / Input TSFS[2] TSFS[3] TSFS[4] TSCK[1] / MTSCK Output / Input TSCK[2] TSCK[3] TSCK[4] Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER F1 TSIG[1:4]: Transmit Side System Signaling for Link The signaling bits are input on these pins ...
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... IDT82P2284 Name Type Pin No. OSCI Input OSCO Output CLK_SEL[0] Input CLK_SEL[1] CLK_SEL[2] CLK_GEN_1.544 Output CLK_GEN_2.048 Output REFA_OUT Output REFB_OUT Output Input RESET GPIO[0] Output / Input GPIO[1] THZ Input Output INT REFR Output Note: * This feature is available in ZB revistion only. Pin Description ...
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... IDT82P2284 Name Type Pin No. CS Input A[0] Input A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] D[0] / SDO Output / Input D[1] D[2] D[3] D[4] D[5] D[6] D[7] MPM Input SDI Input SCLK Input SPIEN Input Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER N10 CS: Chip Select (Active Low) This pin must be asserted low to enable the microprocessor interface. The signal must be asserted high at least once after power up to clear the internal test modes ...
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... IDT82P2284 Name Type Pin No. TRST Input TMS Input TCK Input TDI Input TDO High-Z VDDDIO Power VDDDC Power VDDAR[1] Power VDDAR[2] VDDAR[3] VDDAR[4] VDDAT[1] Power VDDAT[2] VDDAT[3] VDDAT[4] VDDAX[1] Power VDDAX[2] VDDAX[3] VDDAX[4] Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER ...
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... IDT82P2284 Name Type Pin No. VDDAP Power VDDAB Power GNDA Ground GNDD Ground IC - Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER A13 VDDAP: 3.3 V Power Analog PLL D12 VDDAB: 3.3 V Power Analog Bias B3 GNDA: Analog Ground B6 B10 B11 C10 D10 F13 ...
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... IDT82P2284 Name Type Pin No B1, C1, C2, D1, D2, E2, E3, E4, E16, F14, F16, G14, H3, H4, H13, H16, J3, J4, J13, J16, K3, K4, K16, L2, L3, L4, L13, L16, M1, M2, M3, M4, M13, N1, N2, N8, N14, N15, R12, R16, T15, T16 Pin Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER ...
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... IDT82P2284 3 FUNCTIONAL DESCRIPTION The IDT82P2284 is a highly featured single device solution for T1/ E1/J1 trunks. Each link of the IDT82P2284 can be independently config- ured. The configuration is performed through an SPI or parallel micro- processor interface. LINE INTERFACE - RECEIVE PATH In the receive path, the signals from the line side are coupled into the RTIPn and RRINGn pins and pass through an Impedance Termina- tor ...
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... To facilitate the testing and diagnostic functions, Analog Loopback, Remote Digital Loopback, Remote Loopback, Local Digital Loopback, Payload Loopback and System Loopback are also integrated in the IDT82P2284. A programmable pseudo random bit sequence can be generated in receive/transmit direction and detected in the opposite direction for testing purpose. ...
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... IDT82P2284 3 MODE SELECTION Each link in the IDT82P2284 can be configured as a duplex T1 transceiver duplex E1 transceiver duplex J1 transceiver. When mode, Super Frame (SF), Extended Super Frame (ESF), T1 Digital Multiplexer (T1 DM) and Switch Line Carrier - 96 (SLC-96) fram- Table 1: Operating Mode Selection ...
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... IDT82P2284 3.2 RECEIVER IMPEDANCE MATCHING The receiver impedance matching can be realized by using internal impedance matching circuit or external impedance matching circuit. When the R_TERM[2] bit is ‘0’, the internal impedance matching circuit is enabled. 100 Ω, 110 Ω, 75 Ω or 120 Ω internal impedance matching circuit can be selected by the R_TERM[1:0] bits. ...
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... IDT82P2284 DSX cross connect point DSX cross connect point Table 4: Related Bit / Register In Chapter 3.2 Bit R_TERM[2:0] Transmit And Receive Termination Configuration MG[1:0] Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER RTIPn RRINGn R RTIPn RRINGn Figure 3. Monitoring Receive Path TTIPn TRINGn R RTIPn RRINGn Figure 4 ...
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... IDT82P2284 3.3 ADAPTIVE EQUALIZER The Adaptive Equalizer can remove most of the signal distortion due to intersymbol interference caused by cable attenuation and distor- tion. Usually, the Adaptive Equalizer is off in short haul applications and long haul applications, which is configured by the EQ_ON bit. The peak detector keeps on measuring the peak value of the incoming signals during a selectable observation period ...
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... IDT82P2284 3.6 RECEIVE JITTER ATTENUATOR The Receive Jitter Attenuator of each link can be chosen to be used or not. This selection is made by the RJA_E bit. The Jitter Attenuator consists of a FIFO and a DPLL, as shown in Figure 5. Jittered Data FIFO 32/64/128 write pointer Jittered Clock DPLL Figure 5. Jitter Attenuator The FIFO is used as a pool to buffer the jittered input data, then the data is clocked out of the FIFO by a de-jittered clock ...
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... IDT82P2284 3.7 DECODER 3.7.1 LINE CODE RULE 3.7.1 Mode In T1/J1 mode, the AMI and B8ZS line code rules are provided. The selection is made by the R_MD bit. 3.7.1.2 E1 Mode In E1 mode, the AMI and HDB3 line code rules are provided. The selection is made by the R_MD bit. ...
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... IDT82P2284 clock RTIPn RRINGn clock RTIPn 2 RRINGn 1 clock RTIPn 1 RRINGn 2 Figure 8. HDB3 Code Violation & Excessive Zero Error 3.7.3 LOS DETECTION The Loss of Signal (LOS) Detector monitors the amplitude and den- sity of the received signal. When the received signal is below an ampli- tude for continuous intervals, the LOS is detected. When the received signal is above the amplitude and the density of marks meets the requirement, the LOS is cleared ...
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... IDT82P2284 Table 9: LOS Condition In T1/J1 Mode Loss of Signal in T1/J1 Mode ANSI T1.231 Amplitude below 800 mVpp LOS Detected Continuous Intervals 175 bits Amplitude above 1 Vpp LOS 12.5% (16 marks in a hopping Cleared Mark Density 128-bit window **) with less than 100 continuous zeros Note: * The set in the LOS[4:0] bits. ...
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... IDT82P2284 Table 11: Related Bit / Register In Chapter 3.7 Bit R_MD EXZ_ERR EXZ_DEF CNT_MD CNT_TRF CNTL[7:0] CNTH[7:0] CV_IS EXZ_IS CNTOV_IS CV_IE EXZ_IE CNT_IE LAC RAISE LOS_S LOS_IES LOS_IS LOS_IE LOS[4:0] Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Register Receive Configuration 0 Maintenance Function Control 2 ...
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... IDT82P2284 3.8 FRAME PROCESSOR 3.8.1 T1/J1 MODE In T1/J1 mode, the Frame Processor searches for the frame align- ment patterns in the standard Super-Frame (SF), Extended Super- Frame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96 (SLC-96) framing formats. The T1 DM and SLC-96 formats are only sup- ported in T1 mode. The Frame Processor acquires frame alignment per ITU-T requirement ...
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... IDT82P2284 3.8.1.1.2 Extended Super Frame (ESF) Format The structure of T1/J1 ESF is illustrated in Table 13. The ESF is made frames. Each frame consists of one overhead bit (F-bit) and 24 8-bit channels. The F-bit in Frame (4n) (0<n<7) is for Frame Alignment; the F-bit in Frame (2n-1) (0<n<13) is for Data Link; and the F-bit in Frame (4n-2) (0< ...
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... IDT82P2284 3.8.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) The structure illustrated in Table 14. The made frames. Each frame consists of one overhead bit (F-bit) and 24 8-bit channels. Except for channel 24, all other channels carry data. Channel 24 should be ‘0DY11101’. Its Frame Alignment Pattern is ‘ ...
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... IDT82P2284 3.8.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) The structure of SLC-96 is illustrated in Table 15. The SLC-96 is made SFs, but some F-bit are used as Concentrator Bits, Spoiler Bits, Maintenance Bits, Alarm Bits and Switch Bits. Each frame consists of one overhead bit (F-bit) and 24 8-bit channels. Its Frame Alignment Pattern is ‘ ...
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... IDT82P2284 3.8.1.2 Error Event And Out Of Synchronization Detection After the frame is in synchronization, the Frame Processor contin- ues to monitor the received data stream to detect errors and judge out of synchronization. 3.8.1.2.1 Super Frame (SF) Format In SF format, two kinds of errors are detected: 1. Severely Ft Bit Error: Each received Ft bit is compared with the expected one (refer to Table 12) ...
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... IDT82P2284 Once resynchronized, if the new-found F bit position differs from the previous one, the change of frame alignment event is generated. This event is captured by the COFAI bit and is forwarded to the Perfor- mance Monitor. 3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only) In SLC-96 format, the Concentrator bits, Maintenance bits, Alarm bits and Switch bits are all extracted to the RDL0, RDL1 & ...
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... IDT82P2284 Table 17: Related Bit / Register In Chapter 3.8.1 Bit UNFM REFEN REFR REFCRCE MIMICC M2O[1:0] DDSC OOFV MIMICI EXCRCERI OOFI RMFBI SFEI BEEI FERI COFAI OOFE RMFBE SFEE BEEE FERE COFAE C[11:1] M[3:1] A[2:1] S[4:1] SCAI SCSI SCMI SCCI SCDEB SCAE SCSE SCME SCCE Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER ...
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... IDT82P2284 3.8.2 E1 MODE In E1 mode, the Frame Processor searches for Basic Frame syn- chronization, CRC Multi-frame synchronization, and Channel Associated Signaling (CAS) Multi-frame synchronization in the received data stream. Figure 9 shows the searching process. Once the frame is synchronized, the Frame Processor keeps on monitoring the received data stream. If there are any framing bit errors, ...
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... IDT82P2284 search for Basic Fframe alignment patten > 914 CRC search for CRC Multi-Frame errors in alignment pattern if CRCEN = one 1 (refer to CRC Multi-Frame) second Start 8ms and 400ms timer find 2 CRC Multi-Frame alignment patterns within 8ms, with the interval time of each pattern being a ...
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... IDT82P2284 3.8.2.1 Synchronization Searching 3.8.2.1.1 Basic Frame The algorithm used to search for the E1 Basic Frame alignment pattern (as shown in Figure 10) meets the ITU-T Recommendation G.706 4.1.2 and 4.2. Generally performed by detecting a successive FAS/NFAS/ FAS sequence. If STEP 2 is not met, a new searching will start after the following frame is skipped ...
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... IDT82P2284 3.8.2.1.2 CRC Multi-Frame The CRC Multi-Frame is provided to enhance the ability of verifying the data stream. The structure of TS0 of the CRC Multi-Frame is illus- trated in Table 18. A CRC Multi-Frame consists of 16 continuous Basic Frames (No. 0 – 15) which are numbered from a Basic Frame with FAS. Each CRC Multi-Frame can be divided into two Sub Multi-Frames (SMF I & ...
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... IDT82P2284 3.8.2.1.3 CAS Signaling Multi-Frame After the Basic Frame has been synchronized, the Frame Proces- sor starts to search for CAS Signaling Multi-Frame alignment signal if the CASEN bit is ‘1’. The Signaling Multi-Frame alignment pattern is located in the high nibble (Bit 1 ~ Bit 4) of TS16. Its pattern is ‘0000’. When the pattern is ...
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... IDT82P2284 10. NT CRC Error (per ETS 300 233): If the 4-bit Sa6 codeword of a CRC Sub Multi-Frame is matched with ‘0010’ or ‘0011’, the Network Terminal CRC Error event is generated. This error event is captured by the TCRCEI bit and is forwarded to the Performance Monitor. ...
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... IDT82P2284 pared if the Sa6SYN bit is ‘1’ matched code is detected, the corresponding indication bit in the Sa6 Code Indication register will be set. 3.8.2.4 V5.2 Link The V5.2 link ID signal, i.e., 2 out of 3 sliding Sa7 bits being logic 0, is detected with the indication in the V52LINKV bit. This detection is dis- abled when the Basic Frame is out of synchronization ...
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... IDT82P2284 Table 21: Related Bit / Register In Chapter 3.8.2 Bit Register UNFM REFEN FRMR Mode 0 REFCRCE REFR CRCEN C2NCIWCK CASEN WORDERR FRMR Mode 1 CNTNFAS BIT2C SMFASC TS16C OOFV OOCMFV OOOFV FRMR Status C2NCIWV OOSMFV EXCRCERI C2NCIWI OOFI FRMR Interrupt Indication 0 OOCMFI OOSMFI OOOFI OOFE ...
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... IDT82P2284 3.9 PERFORMANCE MONITOR 3.9.1 T1/J1 MODE Several internal counters are used to count different events for per- formance monitoring. For different framing format, the counters are used differently. The overflow of each counter is reflected by an Overflow Indi- cation Bit, and can trigger an interrupt if the corresponding Overflow Interrupt Enable Bit is set ...
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... IDT82P2284 Table 23: Related Bit / Register In Chapter 3.9.1 Bit LCV[15:0] FER[11:0] COFA[2:0] OOF[4:0] PRGD[15:0] CRCE[9:0] DDSE[9:0] LCVOVI FEROVI COFAOVI OOFOVI PRGDOVI CRCOVI DDSOVI LCVOVE FEROVE COFAOVE OOFOVE PRGDOVE CRCOVE DDSOVE LINKSEL[1:0] ADDR[3:0] DATA[7:0] UPDAT AUTOUPD Note means Indirect Register in the Performance Monitor function block. ...
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... IDT82P2284 3.9.2 E1 MODE Several internal counters are used to count different events for per- formance monitoring. The overflow of each counter is reflected by an Overflow Indication Bit, and can trigger an interrupt if the corresponding Overflow Interrupt Enable Bit is set. This is shown in Table 24. These internal counters are indirect registers, and can only be accessed through other direct registers ...
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... IDT82P2284 Table 25: Related Bit / Register In Chapter 3.9.2 Bit LCV[15:0] FER[11:0] CRCE[9:0] FEBE[9:0] COFA[2:0] OOF[4:0] PRGD[15:0] TFEBE[9:0] TCRCE[9:0] LCVOVI FEROVI CRCOVI FEBEOVI COFAOVI OOFOVI PRGDOVI TFEBEOVI TCRCOVI LCVOVE FEROVE CRCOVE FEBEOVE COFAOVE OOFOVE PRGDOVE TFEBEOVE TCRCOVE LINKSEL[1:0] ADDR[3:0] DATA[7:0] UPDAT AUTOUPD Note means Indirect Register in the Performance Monitor function block. ...
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... IDT82P2284 3.10 ALARM DETECTOR 3.10.1 T1/J1 MODE The RED alarm, Yellow alarm and Blue alarm are detected in this block (refer to Table 26). Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria Declare Condition The out of SF/ESF/T1 DM/SLC-96 syn- RED Alarm chronization status persists Nx40 ms. Here (per T1.403, ‘ ...
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... IDT82P2284 Table 27: Related Bit / Register In Chapter 3.10.1 Bit REDDTH[7:0] REDCTH[7:0] YELDTH[7:0] YELCTH[7:0] AISDTH[7:0] AISCTH[7:0] RED YEL AIS REDI YELI AISI REDE YELE AISE Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Register RED Declare Threshold RED Clear Threshold Yellow Declare Threshold Yellow Clear Threshold ...
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... IDT82P2284 3.10.2 E1 MODE The Remote alarm, Remote Signaling Multi-Frame alarm, RED alarm, AIS alarm, AIS in TS16 and LOS in TS16 are detected in this block. The Remote Alarm Indication bit is the A bit (refer to Table 18 detected on the base of Basic frame synchronization. The criteria of Remote alarm detection are defined by the RAIC bit. If the RAIC bit is ‘ ...
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... IDT82P2284 3.11 HDLC RECEIVER The HDLC Receiver extracts the HDLC/SS7 data stream from the selected position and processes the data according to the selected mode. 3.11.1 HDLC CHANNEL CONFIGURATION In T1/J1 mode ESF & formats, three HDLC Receivers (#1, #2 & #3) per link are provided for HDLC extraction from the received data stream. In T1/J1 mode SF & ...
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... IDT82P2284 - The data between the opening flag and the closing flag is less than 5 bytes (including the FCS, excluding the flags); - The extracted HDLC packet does not consist of an integral num- ber of octets (Hex) abort sequence is received; - Address is not matched if the address comparison is enabled. ...
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... IDT82P2284 3.11.2.2 SS7 Mode In SS7 mode, there are three kinds of signaling units - MSU, LSSU and FISU (refer to Figure 14). Their opening flag and closing flag are Flag FCS Signaling Field one byte two bytes n bytes (n>1) '01111110' Flag FCS one byte two bytes '01111110' After the stuffed zero (the zero following five consecutive ’ ...
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... IDT82P2284 means there is an interrupt. The interrupt will be reported by the INT pin if its Interrupt Enable bit is ‘1’. Table 31: Related Bit / Register In Chapter 3.11.2 Bit RHDLCM ADRM[1:0] RHDLC1 Control Register / RHDLC2 Control Register / RHDLC3 Control RRST FISUFIL LSSUFIL HA[7:0] RHDLC1 High Address / RHDLC2 High Address / RHDLC3 High Address ...
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... IDT82P2284 3.12 BIT-ORIENTED MESSAGE RECEIVER (T1/J1 ONLY) The Bit-Oriented Message (BOM) can only be received in the ESF format in T1/J1 mode. The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of the F-bit in the ESF format (refer to Table 13). The six ‘X’s represent the message. The BOM is declared only when the pattern is matched and the received message is identical 4 out of 5 consecutive times or 8 out of 10 consecutive times and differs from the previous message ...
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... IDT82P2284 3.14 ELASTIC STORE BUFFER In Receive Clock Slave mode and Receive Multiplexed mode basic-frame depth Elastic Store Buffer is used to synchronize the incom- ing frames to the (Multiplexed) Receive Side System Clock derived from the RSCKn/MRSCK pin, and to the (Multiplexed) Receive Side System Frame Pulse derived from the RSFSn/MRSFS pin ...
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... IDT82P2284 Channel 24 RSDn MRSDA(MRSDB) RSIGn MRSIGA(MRSIGB) 3.15.2 E1 MODE In Signaling Multi-Frame, the signaling bits are located in TS16 (refer to Figure 11), which are Channel Associated Signalings (CAS). The signaling codewords (ABCD) are clocked out on the RSIGn/ MRSIGA(MRSIGB) pins. They are in the lower nibble of the timeslot with its corresponding data serializing on the RSDn/MRSDA(MRSDB) pins (as shown in Figure 16) ...
Page 63
... IDT82P2284 Table 35: Related Bit / Register In Chapter 3.15 Bit EXTRACT A,B,C,D DEB FREEZE SIGF (T1/J1 only) SIGE COSI[X] (1 ≤ X ≤ T1/J1) (1 ≤ X ≤ E1) ADDRESS[6:0] RWN D[7:0] BUSY Note means Indirect Register in the Receive CAS/RBS Buffer function block. Functional Description QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER ...
Page 64
... IDT82P2284 3.16 RECEIVE PAYLOAD CONTROL Different test patterns can be inserted in the received data stream or the received data stream can be extracted to the PRBS Generator/ Detector for test in this block. To enable all the functions in the Receive Payload Control, the PCCE bit must be set to ‘1’. ...
Page 65
... IDT82P2284 read from or written into the specified indirect register is determined by the RWN bit and the data is in the D[7:0] bits. The access status is indi- Table 38: Related Bit / Register In Chapter 3.16 Bit PCCE SIGFIX (T1/J1 only) POL (T1/J1 only) ABXX (T1/J1 only) TESTEN PRBSDIR PRBSMODE[1:0] TEST STRKEN ...
Page 66
... IDT82P2284 3.17 RECEIVE SYSTEM INTERFACE The Receive System Interface determines how to output the received data stream to the system backplane. The data from the four links can be aligned with each other or be output independently. The tim- ing clocks and framing pulses can be provided by the system backplane or obtained from the far end ...
Page 67
... IDT82P2284 3.17.1.1.2 Receive Clock Master Fractional T1/J1 Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode is that the RSCKn is a gapped 1.544 MHz clock (no clock signal during the selected position). The RSCKn is gapped during the F-bit if the FBITGAP bit is set to ‘ ...
Page 68
... IDT82P2284 1.544 CH1 CH2 F Mb/s 2.048 TS0 TS1 TS2 Mb/s filler the 8th bit Figure 19. T1/ Format Mapping - Continuous Channels Mode In the Receive Clock Slave mode, the timing signal on the RSCKn pin and the framing pulse on the RSFSn pin to output the data on the RSDn pin are provided by the system side. When the RSLVCK bit is set to ‘ ...
Page 69
... IDT82P2284 MRSIGA(MRSIGB) pin are always per-channel aligned with the data on the RSDn/MRSDA(MRSDB) pin. Receive Clock Slave mode / Receive Multiplexed mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Receive Clock Master mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Figure 20. No Offset When & Receive Path ...
Page 70
... IDT82P2284 Receive Clock Slave mode / Receive Multiplexed mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Receive Clock Master mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSDA(B) Figure 22. No Offset When & Receive Path Receive Clock Slave mode / Receive Multiplexed mode: RSFSn / MRSFS ...
Page 71
... IDT82P2284 3.17.2 E1 MODE In E1 mode, the Receive System Interface can be set in Non-multi- plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the RSDn pin is used to output the received data from each link at the bit rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data from the four links is byte interleaved to form one high speed data stream and output on the MRSDA1 (MRSDB1) pins at the bit rate of 8 ...
Page 72
... IDT82P2284 RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled on its first active edge. In the Receive Clock Slave mode, the RSFSn asserts at a rate of integer multiple of 125 µs to indicate the start of a frame. The active polarity of the RSFSn is selected by the FSINV bit. If the pulse on the RSFSn pin is not an integer multiple of 125 µ ...
Page 73
... IDT82P2284 3.18 TRANSMIT SYSTEM INTERFACE The Transmit System Interface determines how to input the data to the device. The data input to the four links can be aligned with each other or input independently. The timing clocks and framing pulses can be provided by the system backplane or obtained from the processed data of each link ...
Page 74
... IDT82P2284 3.18.1.1.1 Transmit Clock Master Full T1/J1 Mode Besides all the common functions described in the Transmit Clock Master mode, the special feature in this mode is that the TSCKn is a standard 1.544 MHz clock, and the data in the F-bit and all 24 channels in a standard T1/J1 frame are clocked in by the TSCKn. ...
Page 75
... IDT82P2284 the 8th bit discarded 2.048 TS0 TS1 TS2 Mb/s 1.544 CH1 CH2 F Mb/s Figure 26 T1/J1 Format Mapping - Continuous Channels Mode In the Transmit Clock Slave mode, the timing signal on the TSCKn pin and the framing pulse on the TSFSn pin to input the data on the TSDn pin are provided by the system side. When the TSLVCK bit is set to ‘ ...
Page 76
... IDT82P2284 3.18.1.4 Offset Bit offset and channel offset are both supported in all the operating modes. The offset is between the framing pulse on the TSFSn/MTSFS pin and the start of the corresponding frame input on the TSDn/ MTSDA(MTSDB) pin. The signaling Transmit Clock Slave mode / Transmit Multiplexed mode: ...
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... IDT82P2284 Transmit Clock Slave mode / Transmit Multiplexed mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSDA(B) Transmit Clock Master mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSDA(B) Figure 29. No Offset When & Transmit Path Transmit Clock Slave mode / Transmit Multiplexed mode: TSFSn / MTSFS ...
Page 78
... IDT82P2284 3.18.2 E1 MODE In E1 mode, the Transmit System Interface can be set in Non-multi- plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the TSDn pin is used to input the data to each link at the bit rate of 2.048 Mb/s. While in the Multiplexed Mode, the data is byte interleaved from one high speed data stream and inputs on the MTSDA1 (MTSDB1) pins at the bit rate of 8 ...
Page 79
... IDT82P2284 the EDGE bit determines the active edge to sample the data on the TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled on its first active edge. In the Transmit Clock Slave mode, the TSFSn can indicate the Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica- tions are selected by the FSTYP bit ...
Page 80
... IDT82P2284 3.19 TRANSMIT PAYLOAD CONTROL Different test patterns can be inserted in the data stream to be transmitted or the data stream to be transmitted can be extracted to the PRBS Generator/Detector for test in this block. To enable all the functions in the Transmit Payload Control, the PCCE bit must be set to ‘1’. ...
Page 81
... IDT82P2284 3.20 FRAME GENERATOR 3.20.1 GENERATION 3.20.1 Mode In T1/J1 mode, the data to be transmitted can be generated as Super-Frame (SF), Extended Super-Frame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96 (SLC-96) format. 3.20.1.1.1 Super Frame (SF) Format The SF is generated when the FDIS bit is ‘0’. The Frame Alignment Pattern (‘100011011100’ for T1 / ‘ ...
Page 82
... IDT82P2284 the mimic pattern is the same as the F-bit. The mimic pattern insertion is for diagnostic purpose. The Yellow alarm signal will be manually inserted in the data stream to be transmitted when the XYEL bit is set, or the Yellow alarm signal will be inserted automatically by setting the AUTOYELLOW bit when Red alarm is declared in the received data stream ...
Page 83
... IDT82P2284 3.20.1.2 E1 Mode In E1 mode, the Frame Generator can generate Basic Frame, CRC-4 Multi-Frame and Channel Associated Signaling (CAS) Multi- Frame. The Frame Generator can also transmit alarm indication signal when special conditions occurs in the received data stream. Interna- tional bits, National bits and Extra bits replacements and data inversions are all supported in the Frame Generator ...
Page 84
... IDT82P2284 3.20.1.2.1 Interrupt Summary In E1 mode, the interrupt is summarized in Table 49. When there are conditions meeting the interrupt sources, the corre- sponding Interrupt Indication bit will be set. When the Interrupt Indication Table 49: Interrupt Summary In E1 Mode Interrupt Sources At the first bit of each FAS. ...
Page 85
... IDT82P2284 Table 50: Related Bit / Register In Chapter 3.20.1.2 Bit FDIS GENCRC CRCM SIGEN SiDIS FEBEDIS XDIS FAS1INV FASALLINV NFASINV CRCPINV CASPINV CRCINV Si[1] Si[0] REMAIS AUTOYELLOW G706RAI MFAIS TS16LOS TS16AIS SaX[1:4] (‘X’ is from SaXEN (‘X’ is from OOCMFV X[0:2] FASI BFI MFI SMFI ...
Page 86
... IDT82P2284 3.20.2 HDLC TRANSMITTER The HDLC Transmitter inserts the data into the selected position to form HDLC or SS7 packet data stream. 3.20.2.1 HDLC Channel Configuration In T1/J1 mode ESF & formats, three HDLC Transmitters (#1, #2 & #3) per link are provided for HDLC insertion to the data stream to be transmitted. In T1/J1 mode SF & ...
Page 87
... IDT82P2284 3.20.2.3 Interrupt Summary In both of the two HDLC modes, when the data in the FIFO is below the lower threshold set by the LL[1:0] bits, it will be indicated by the RDY bit. When there is a transition (from ‘0’ to ‘1’) on the RDY bit, the RDYI bit will be set. In this case, if enabled by the RDYE bit, an interrupt will be reported by the INT pin ...
Page 88
... IDT82P2284 3.20.3 AUTOMATIC PERFORMANCE REPORT MESSAGE (T1/ J1 ONLY) The Automatic Performance Report Message (APRM) can only be transmitted in the ESF format in T1/J1 mode. Five kinds of events are counted every second in the APRM: 1. The Bipolar Violation (BPV) Error / HDB3 Code Violation (CV) Error event detected in the B8ZS/HDL3/AMI Decoder; ...
Page 89
... IDT82P2284 Table 55: Related Bit / Register In Chapter 3.20.3 Bit Register AUTOPRM CRBIT RBIT APRM Control U1BIT U2BIT LBBIT 3.20.4 BIT-ORIENTED MESSAGE TRANSMITTER (T1/J1 ONLY) The Bit Oriented Message (BOM) can only be transmitted in the ESF format in T1/J1 mode. The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of the F-bit in the ESF format. The six ‘ ...
Page 90
... IDT82P2284 3.21 TRANSMIT BUFFER Transmit Buffer can be used in the circumstances that backplane timing is different from the line side timing in Transmit Slave mode. The function of timing option is also integrated in this block. The source of the transmit clock can be selected in the recovered clock from the line side, the processed clock from the backplane or the master clock generated by the clock generator ...
Page 91
... IDT82P2284 3.23 TRANSMIT JITTER ATTENUATOR The Transmit Jitter Attenuator of each link can be chosen to be used or not. This selection is made by the TJA_E bit. The Jitter Attenuator consists of a FIFO and a DPLL, as shown in Figure 5. The FIFO is used as a pool to buffer the jittered input data, then the data is clocked out of the FIFO by a de-jittered clock ...
Page 92
... T1 - 399 ~ 533 533 ~ 655 655 ft E1 Mode 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.6 -0.4 -0.2 0 Time In Unit Intervals Figure 33. E1 Waveform Template TTIPn IDT82P2284 TRINGn = 75 Ω or 120 Ω (+ 5%) LOAD PULS[3: 0.6 0.2 0 LOAD OUT March 22, 2004 ...
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... IDT82P2284 To meet the template, two preset waveform templates are provided corresponding to two kinds of cable impedance. The selection is made by the PULS[3:0] bits. In internal impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0] bits should be set to ‘0000’; if the cable impedance is 120 Ω, the PULS[3:0] bits should be set to ‘0001’. In external impedance matching mode, for both 75 Ω ...
Page 94
... IDT82P2284 Table 62: Transmit Waveform Value For E1 75 Ω Sample 1 0000000 0000000 Sample 2 0000000 0000000 Sample 3 0000000 0000000 Sample 4 0001100 0000000 Sample 5 0110000 0000000 Sample 6 0110000 0000000 Sample 7 0110000 0000000 Sample 8 0110000 0000000 Sample 9 0110000 0000000 Sample 10 0110000 0000000 Sample 11 ...
Page 95
... IDT82P2284 Table 64: Transmit Waveform Value For T1 0~133 Sample 1 0010111 1000010 Sample 2 0100111 1000001 Sample 3 0100111 0000000 Sample 4 0100110 0000000 Sample 5 0100101 0000000 Sample 6 0100101 0000000 Sample 7 0100101 0000000 Sample 8 0100100 0000000 Sample 9 0100011 0000000 Sample 10 1001010 0000000 Sample 11 1001010 ...
Page 96
... IDT82P2284 Table 66: Transmit Waveform Value For T1 266~399 Sample 1 0011111 1000011 Sample 2 0110001 1000010 Sample 3 0101111 1000001 Sample 4 0101100 0000000 Sample 5 0101011 0000000 Sample 6 0101010 0000000 Sample 7 0101001 0000000 Sample 8 0101000 0000000 Sample 9 0100101 0000000 Sample 10 1010111 0000000 Sample 11 1010011 ...
Page 97
... IDT82P2284 Table 68: Transmit Waveform Value For T1 533~655 Sample 1 0100000 1000011 Sample 2 0111111 1000010 Sample 3 0111000 1000001 Sample 4 0110011 0000000 Sample 5 0101111 0000000 Sample 6 0101110 0000000 Sample 7 0101101 0000000 Sample 8 0101100 0000000 Sample 9 0101001 0000000 Sample 10 1011111 0000000 Sample 11 1011110 ...
Page 98
... IDT82P2284 Table 70: Transmit Waveform Value For DS1 0 dB LBO Sample 1 0010111 1000010 Sample 2 0100111 1000001 Sample 3 0100111 0000000 Sample 4 0100110 0000000 Sample 5 0100101 0000000 Sample 6 0100101 0000000 Sample 7 0100101 0000000 Sample 8 0100100 0000000 Sample 9 0100011 0000000 Sample 10 1001010 0000000 ...
Page 99
... IDT82P2284 Table 72: Transmit Waveform Value For DS1 -15.0 dB LBO Sample 1 0000000 0110101 Sample 2 0000000 0110011 Sample 3 0000000 0110000 Sample 4 0000001 0101101 Sample 5 0000100 0101010 Sample 6 0001000 0100111 Sample 7 0001110 0100100 Sample 8 0010100 0100001 Sample 9 0011011 0011110 Sample 10 0100010 0011100 Sample 11 ...
Page 100
... IDT82P2284 3.25 LINE DRIVER The Line Driver can be set to High-Z for redundant application. The following ways will set the drivers to High-Z: 1. Setting the THZ pin to high will globally set all the Line Drivers to High-Z; 2. When there is no clock input on the OSCI pin, all the Line Drivers will be High-Z (no clock means this: the input on the OSCI pin is in high/ low level, or the duty cycle is less than 30% or larger than 70%) ...
Page 101
... IDT82P2284 3.26 TRANSMITTER IMPEDANCE MATCHING In T1/J1 mode, the transmitter impedance matching can be real- ized by using internal impedance matching circuit. 100 Ω, 110 Ω, 75 Ω or 120 Ω internal impedance matching circuit can be selected by the T_TERM[1:0] bits. The external impedance circuitry is not supported in T1/J1 mode mode, the transmitter impedance matching can be realized by using internal impedance matching circuit or external impedance matching circuit. When the T_TERM[2] bit is ‘ ...
Page 102
... IDT82P2284 3.27 TESTING AND DIAGNOSTIC FACILITIES 3.27.1 PRBS GENERATOR / DETECTOR The PRBS Generator / Detector generates test pattern to either the transmit or receive direction, and detects the pattern in the opposite direction. The direction is determined by the PRBSDIR bit. The pattern can be generated or detected in unframed mode, in 8-bit-based mode or in 7-bit-based mode ...
Page 103
... LOOPBACK System Loopback, Payload Loopback, Local Digital Loopback 1 & 2, Remote Loopback and Analog Loopback are all supported in the IDT82P2284. Their routes are shown in the Functional Block Diagram. 3.27.2.1 System Loopback The System Loopback can only be implemented when the Receive System Interface and the Transmit System Interface are in different Non-multiplexed operating modes (one in Clock Master mode and the other in Clock Slave mode) ...
Page 104
... IDT82P2284 TSD1 / MTSDA1 TSIG1 / MTSIGA1 Transmit System TSFS1 / MTSFS Interface TSCK1 / MTSCK RSCK1 / MRSCK RSFS1 / MRSFS Receive System RSIG1 / MRSIGA1 Interface RSD1 / MRSDA1 TSDn / MTSDB1 TSIGn / MTSIGB1 Transmit System Interface TSFSn TSCKn RSCKn RSFSn Receive System Interface RSIGn / MRSIGB1 RSDn / MRSDB1 ...
Page 105
... IDT82P2284 Table 78: Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3 Bit SRLP SLLP DLLP RLP DLP ALP GSUBST[2:0] SUBST[2:0] MON[3:0] Note means Indirect Register in the Transmit Payload Control function block. QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Register Maintenance Function Control 0 TPLC Configuration Channel Control (for T1/J1) / Timeslot Control (for E1) G ...
Page 106
... IDT82P2284 3.28 INTERRUPT SUMMARY When the INT pin is asserted low, it means at least one interrupt has occurred in the device. Reading the Timer Interrupt Indication regis- ter and Interrupt Requisition Link ID register will find whether the timer interrupt occurs or in which link the interrupt occurs. ...
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... IDT82P2284 4 OPERATION 4.1 POWER-ON SEQUENCE To power on the device, the following sequence should be followed: 1. Apply ground; 2. Apply 3 Apply 1.8 V. 4.2 RESET When the device is powered-up, all the registers contain random values. The hardware reset pin RESET must be asserted low during the power-up and the low signal should last at least initialize the device ...
Page 108
... IDT82P2284 4.4 MICROPROCESSOR INTERFACE The microprocessor interface provides access to read and write the registers in the device. The interface consists of Serial Peripheral Inter- face (SPI) and parallel microprocessor interface SCLK Instruction SDI A11 A10 SDO SCLK ...
Page 109
... In this mode, the interface is compatible with the Motorola and the Intel microprocessor, which is selected by the MPM pin. The IDT82P2284 uses separate address bus and data bus. The mode selec- tion and the interfaced pin are tabularized in Table 80. Table 80: Parallel Microprocessor Interface ...
Page 110
... IDT82P2284 4.5 INDIRECT REGISTER ACCESS SCHEME In Receive CAS/RBS Buffer, Receive Payload Control and Trans- mit Payload Control blocks, per-channel/per-timeslot indirect register is accessed by using an indirect register access scheme. 4.5.1 INDIRECT REGISTER READ ACCESS The indirect register read access is as follows: - Read the BUSY bit in the Access Status register to confirm the bit is ‘ ...
Page 111
... IDT82P2284 5 PROGRAMMING INFORMATION 5.1 REGISTER MAP In the ‘Reg’ column, the ‘X’ represents corresponding to the four links. 5.1.1 T1/J1 MODE 5.1.1.1 Direct Register T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) 001 ID7 ID6 002 ~ 003 - - 004 - - 005 - - 006 - - 007 - - 008 - - 009 - - 00A - - 00B - - 00C ~ 00D ...
Page 112
... IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X34 - DAC_IE TJA_IE X35 - - X36 - - X37 - - X38 - TJITT6 TJITT5 X39 - RJITT6 RJITT5 X3A - - X3B - DAC_IS TJA_IS X3C CNTH[7] CNTH[6] CNTH[5] X3D CNTL[7] CNTL[6] CNTL[5] X3E - - X3F - - X40 IBCD RBOC ALARM X41 THDLC3 THDLC2 THDLC1 X42 ...
Page 113
... IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X68 ~ X6A - - X6B - - X6C - - X6D - - X6E - - X6F - - X70 - - X71 - - X72 - - X73 - - X74 - - X75 IBC7 IBC6 IBC5 X76 - - X77 - - X78 ACT7 ACT6 ACT5 X79 DACT7 DACT6 DACT5 X7A - - X7B - - X7C - - X7D - - X7E TRKCODE TRKCODE TRKCODE 7 6 X7F ...
Page 114
... IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X98 DAT7 DAT6 DAT5 X99 DAT7 DAT6 DAT5 X9A DAT7 DAT6 DAT5 X9B - - X9C - - X9D - - X9E - - X9F - - XA0 - - XA1 HA7 HA6 HA5 XA2 HA7 HA6 HA5 XA3 HA7 HA6 HA5 XA4 LA7 LA6 LA5 XA5 ...
Page 115
... IDT82P2284 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) XC7 - - XC8 - - XC9 RWN ADDRESS ADDRESS 6 XCA D7 D6 XCB SIGSNAP GSTRKEN ZCS2 XCC - - XCD - - XCE RWN ADDRESS ADDRESS 6 XCF D7 D6 XD0 SIGSNAP GSTRKEN XD1 - - XD2 - - XD3 - - XD4 RWN ADDRESS ADDRESS 6 XD5 D7 D6 XD6 COSI8 COSI7 ...
Page 116
... IDT82P2284 5.1.1.2 Indirect Register PMON Address (Hex) Bit 7 Bit 6 00 CRCE7 CRCE6 CRCE5 FER7 FER6 PRGD7 PRGD6 PRGD5 07 PRGD15 PRGD14 PRGD13 08 LCV7 LCV6 09 LCV15 LCV14 0A DDSE7 DDSE6 RCRB Address (Hex) Bit 7 Bit 6 Bit RPLC Address (Hex) Bit 7 Bit 6 ...
Page 117
... IDT82P2284 5.1.2 E1 MODE 5.1.2.1 Direct Register E1 Reg Bit 7 Bit 6 Bit 5 (Hex) 001 ID7 ID6 ID5 002 ~ - - - 003 004 - - - 005 - - - 006 - - - 007 - - - 008 - - - 009 - - - 00A - - - 00B - - - 00C ~ - - - 00D 00E - LINKSEL1 LINKSEL0 00F DAT7 DAT6 DAT5 010 - - - 011 ~ - - - 01F X20 - - - X21 - - TJITT_TES T X22 - - - X23 - - DFM_ON ...
Page 118
... IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X38 - TJITT6 TJITT5 X39 - RJITT6 RJITT5 X3A - - - X3B - DAC_IS TJA_IS X3C CNTH[7] CNTH[6] CNTH[5] X3D CNTL[7] CNTL[6] CNTL[5] X3E - - - X3F - - - X40 - - ALARM X41 THDLC3 THDLC2 THDLC1 X42 - - - X43 - - - X44 - TSOFF6 TSOFF5 X45 - - - X46 - - - X47 - - - ...
Page 119
... IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X64 - - - X65 - - - X66 - - - X67 - - - X68 - - - X69 - - - X6A - - - X6B - - TS16LOS X6C - - - X6D - - - X6E - - - X6F - - CRCINV X70 - - - X71 - - - X72 - - - X73 - - - X74 ~ - - - X7B X7C - - - X7D - - - X7E TRKCODE7 TRKCODE TRKCODE 6 5 X7F ~ - - - X83 X84 - - - X85 - EVEN ODD X86 - EVEN ...
Page 120
... IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X9B - - - X9C - - - X9D - - - X9E - - - X9F - - - XA0 - - - XA1 HA7 HA6 HA5 XA2 HA7 HA6 HA5 XA3 HA7 HA6 HA5 XA4 LA7 LA6 LA5 XA5 LA7 LA6 LA5 XA6 LA7 LA6 LA5 XA7 - - AUTOFISU XA8 - - AUTOFISU XA9 ...
Page 121
... IDT82P2284 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) XCD - - - XCE RWN ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3 ADDRESS2 ADDRESS1 ADDRESS0 RPLC Access Control XCF XD0 SIGSNAP GSTRKEN - XD1 - - - XD2 - - - XD3 - - - XD4 RWN ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3 ADDRESS2 ADDRESS1 ADDRESS0 RCRB Access Control XD5 D7 D6 ...
Page 122
... IDT82P2284 5.1.2.2 Indirect Register PMON Address (Hex) Bit 7 Bit 6 00 CRCE7 CRCE6 CRCE5 FER7 FER6 PRGD7 PRGD6 PRGD5 07 PRGD15 PRGD14 PRGD13 PRGD12 08 LCV7 LCV6 09 LCV15 LCV14 LCV13 0A TCRCE7 TCRCE6 TCRCE5 TCRCE4 TCRCE3 FEBE7 FEBE6 FEBE5 TFEBE7 TFEBE6 ...
Page 123
... IDT82P2284 TPLC Address (Hex) Bit 7 Bit 6 Bit SUBST2 SUBST1 SUBST0 DTRK7 DTRK6 DTRK5 TEST TEST Programming Information QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Bit 4 Bit 3 Bit 2 Bit 1 SINV OINV EINV G56K DTRK4 DTRK3 DTRK2 DTRK1 - STRKEN ...
Page 124
... IDT82P2284 5.2 REGISTER DESCRIPTION Depending on the operating mode, the registers are configured for T1/J1 or E1. Before setting any other registers, the operating mode should be selected in registers 020H, 120H, 220H and 320H. According to the access method, the registers can be divided into direct registers and indirect registers. In the direct registers, the registers can be divided into global configuration registers and per-link configuration registers ...
Page 125
... Bit Name ID7 Type R Default 0 ID[7:0]: The ID[7:0] bits are pre-set. The ID[7:4] bits represent the IDT82P2284 device. The ID[3:0] bits represent the current version number (‘0001’ is for the first version). T1/J1 Software Reset (004H) Bit No. 7 Bit Name Type Default A write operation to this register will generate a software reset. ...
Page 126
... IDT82P2284 T1/J1 G.772 Monitor Control (005H) Bit No Bit Name Type Default MON[3:0]: These bits determine whether the G.772 Monitor is implemented. When the G.772 Monitor is implemented, these bits select one transmitter or receiver to be monitored by the Link 1. MON[3:0] Monitored Path 0000 No transmitter or receiver is monitored. ...
Page 127
... IDT82P2284 T1/J1 GPIO Control (006H) Bit No. 7 Bit Name Type Default LEVEL[1]: When the GPIO[1] pin is defined as an output port, this bit can be read and written The GPIO[1] pin outputs low level The GPIO[1] pin outputs high level. When the GPIO[1] pin is defined as an input port, this bit can only be read Low level is input on the GPIO[1] pin ...
Page 128
... IDT82P2284 T1/J1 Reference Clock Output Select (007H) Bit No Bit Name Type Reserved Default RO2[1:0]: When no LOS is detected, the REFB_OUT pin outputs a recovered clock from the Clock and Data Recovery function block of one of the four links. The link is selected by these bits: When LOS is detected, the REFB_OUT pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH,...). (This feature is available in ZB revision only) ...
Page 129
... IDT82P2284 T1/J1 Interrupt Requisition Link ID (009H) Bit No. 7 Bit Name Type Default INTn interrupt is generated in the corresponding link least one interrupt is generated in the corresponding link. T1/J1 Timer Interrupt Control (00AH) Bit No. 7 Bit Name Type Default TMOVE Disable the interrupt on the INT pin when the TMOVI bit (b0, T1/J1-00BH) is ‘1’. ...
Page 130
... IDT82P2284 T1/J1 PMON Access Port (00EH) Bit No. 7 Bit Name LINKSEL1 Type Reserved R/W Default LINKSEL[1:0]: These bits select one of the four links. One of the PMON indirect registers of the selected link can be accessed by the microprocessor. ADDR[3:0]: These bits select one of the PMON indirect registers of the selected link to be accessed by the microprocessor. ...
Page 131
... IDT82P2284 T1/J1 Backplane Global Configuration (010H) Bit No. 7 Bit Name Type Reserved Default RSLVCK: This bit is valid when all four links are in the Receive Clock Slave mode Each link uses its own clock signal on the RSCKn pin and framing pulse on the RSFSn pin. ...
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... IDT82P2284 T1/J1 Transmit Jitter Attenuation Configuration (021H, 121H, 221H, 321H) Bit No. 7 Bit Name Type Reserved Default TJITT_TEST The real time interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, T1/J1-038H,...). That is, the current interval between the read and write pointer of the FIFO will be written into the TJITT[6:0] bits (b6~0, T1/J1-038H,...). ...
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... IDT82P2284 T1/J1 Transmit Configuration 0 (022H, 122H, 222H, 322H) Bit No. 7 Bit Name Type Reserved Default T_OFF The transmit path is power up The transmit path is power down. The Line Driver is in high impedance. T_MD: This bit selects the line code rule to encode the data stream to be transmitted. ...
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... IDT82P2284 T1/J1 Transmit Configuration 1 (023H, 123H, 223H, 323H) Bit No. 7 Bit Name Type Reserved Default DFM_ON The Driver Failure Monitor is disabled The Driver Failure Monitor is enabled. T_HZ The Line Driver works normally Set the Line Driver . (The other parts of the transmit path still work normally.) ...
Page 135
... IDT82P2284 T1/J1 Transmit Configuration 2 (024H, 124H, 224H, 324H) Bit No. 7 Bit Name Type Reserved Default SCAL[5:0]: The following setting lists the standard values of normal amplitude in different operating modes. Each step change (one increasing or decreasing from the standard value) will scale the amplitude of the D/A output by a certain offset. These bits are only effective when user programmable arbitrary waveform is used ...
Page 136
... IDT82P2284 T1/J1 Transmit Configuration 3 (025H, 125H, 225H, 325H) Bit No Bit Name DONE RW Type R/W R/W Default 0 0 This register is valid when the PULS[3:0] bits (b3~0, T1/J1-023H,...) are set to ‘11xx’. DONE Disable the read/write operation to the pulse template RAM Enable the read/write operation to the pulse template RAM. ...
Page 137
... IDT82P2284 T1/J1 Transmit Configuration 4 (026H, 126H, 226H, 326H) Bit No Bit Name WDAT6 Type Reserved R/W Default 0 WDAT[6:0]: These bits contain the data to be stored in the pulse template RAM which is addressed by the UI[1:0] bits (b5~4, T1/J1-025H,...) and the SAMP[3:0] bits (b3~0, T1/J1-025H,...). T1/J1 Receive Jitter Attenuation Configuration (027H, 127H, 227H, 327H) Bit No ...
Page 138
... IDT82P2284 T1/J1 Receive Configuration 0 (028H, 128H, 228H, 328H) Bit No. 7 Bit Name Type Reserved Default R_OFF The receive path is power up The receive path is power down. R_MD: This bit selects the line code rule to decode the received data stream The B8ZS decoder is selected. ...
Page 139
... IDT82P2284 T1/J1 Receive Configuration 1 (029H, 129H, 229H, 329H) Bit No Bit Name EQ_ON Type Reserved R/W Default 0 EQ_ON The Equalizer is off in short haul applications The Equalizer long haul applications. LOS[4:0]: A LOS is detected when the incoming signals has “no transitions”, i.e., when the signal level is less than Q dB below nominal for N consecutive pulse intervals ...
Page 140
... IDT82P2284 T1/J1 Receive Configuration 2 (02AH, 12AH, 22AH, 32AH) Bit No Bit Name Type Reserved Default SLICE[1:0]: These two bits define the Data Slicer threshold. = 00: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 40% of the peak amplitude. = 01: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 50% of the peak amplitude. ...
Page 141
... IDT82P2284 T1/J1 Maintenance Function Control 0 (02BH, 12BH, 22BH, 32BH) Bit No Bit Name DLLP Type Reserved R/W Default 0 DLLP Disable the Local Digital Loopback Enable the Local Digital Loopback 1. SLLP Disable the System Local Loopback Enable the System Local Loopback. SRLP Disable the System Remote Loopback. ...
Page 142
... IDT82P2284 T1/J1 Maintenance Function Control 1 (02CH, 12CH, 22CH, 32CH) Bit No Bit Name Type Default LAC: This bit selects the LOS criterion The T1.231 is selected. In short haul application, the LOS is declared when the incoming signal level is less than 800 mVpp for 175 consec- utive bit intervals and is cleared when the incoming signal level is greater than 1 Vpp and has an average mark density of at least 12 ...
Page 143
... IDT82P2284 T1/J1 Maintenance Function Control 2 (031H, 131H, 231H, 331H) Bit No Bit Name BPV_INS Type Reserved R/W Default 0 BPV_INS: A transition from ‘0’ to ‘1’ on this bit generates a single Bipolar Violation (BPV) Error to be inserted to the data stream to be transmitted. This bit must be cleared and set again for the next BPV error insertion. ...
Page 144
... IDT82P2284 T1/J1 Transmit And Receive Termination Configuration (032H, 132H, 232H, 332H) Bit No Bit Name Type Reserved Default T_TERM[2:0]: These bits select the internal impedance of the transmit path to match the cable impedance: = 000: The 75 Ω internal impedance matching is selected. = 001: The 120 Ω internal impedance matching is selected. ...
Page 145
... IDT82P2284 T1/J1 Interrupt Enable Control 1 (034H, 134H, 234H, 334H) Bit No Bit Name DAC_IE Type Reserved R/W Default 0 DAC_IE Disable the interrupt on the INT pin when the DAC_IS bit (b6, T1/J1-03BH,...) is ‘1’ Enable the interrupt on the INT pin when the DAC_IS bit (b6, T1/J1-03BH,...) is ‘1’. ...
Page 146
... IDT82P2284 T1/J1 Interrupt Trigger Edges Select (035H, 135H, 235H, 335H) Bit No Bit Name Type Default DF_IES The DF_IS bit (b2, T1/J1-03AH,...) will be set to ‘1’ when there is a transition from ‘0’ to ‘1’ on the DF_S bit (b2, T1/J1-036H,...). = 1: The DF_IS bit (b2, T1/J1-03AH,...) will be set to ‘1’ when there is any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit (b2, T1/J1- 036H, ...
Page 147
... IDT82P2284 T1/J1 Line Status Register 1 (037H, 137H, 237H, 337H) Bit No Bit Name Type Reserved Default LATT[4:0]: These bits indicate the current gain of the VGA relative peak pulse level. LATT[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 ...
Page 148
... IDT82P2284 T1/J1 Transmit Jitter Measure Value Indication (038H, 138H, 238H, 338H) Bit No Bit Name TJITT6 Type Reserved R Default 0 TJITT[6:0]: When the TJITT_TEST bit (b5, T1/J1-021H,...) is ‘0’, these bits represent the current interval between the read and write pointer of the FIFO. When the TJITT_TEST bit (b5, T1/J1-021H,...) is ‘1’, these bits represent the P-P interval between the read and write pointer of the FIFO since last read. These bits will be cleared if a ’ ...
Page 149
... IDT82P2284 T1/J1 Interrupt Status 0 (03AH, 13AH, 23AH, 33AH) Bit No Bit Name Type Default DF_IS There is no status change on the DF_S bit (b2, T1/J1-036H,...). = 1: When the DF_IES bit (b2, T1/J1-035H,...) is ‘0’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ on the DF_S bit (b2, T1/J1- 036H,...) ...
Page 150
... IDT82P2284 T1/J1 Interrupt Status 1 (03BH, 13BH, 23BH, 33BH) Bit No Bit Name DAC_IS Type Reserved R Default 0 DAC_IS The sum of a pulse template does not exceed the D/A limitation (+63) when more than one UI is used to compose the arbitrary pulse tem- plate The sum of a pulse template exceeds the D/A limitation (+63) when more than one UI is used to compose the arbitrary pulse template. ...
Page 151
... IDT82P2284 T1/J1 EXZ Error Counter H-Byte (03CH, 13CH, 23CH, 33CH) Bit No Bit Name CNTH[7] CNTH[6] Type R R Default 0 0 CNTH[7:0]: These bits, together with the CNTL[7:0] bits, reflect the content in the internal 16-bit EXZ counter. T1/J1 EXZ Error Counter L-Byte (03DH, 13DH, 23DH, 33DH) Bit No ...
Page 152
... IDT82P2284 T1/J1 Interrupt Module Indication 2 (03FH, 13FH, 23FH, 33FH) Bit No Bit Name Type Default LIU interrupt is generated in the Receive / Transmit Internal Termination, Adaptive Equalizer, Data Slicer, CLK&Data Recovery, Receive / Transmit Jitter Attenuator, B8ZS/HDB3/AMI Decoder / Encoder, Waveform Shaper / Line Build Out or Line Driver block. ...
Page 153
... IDT82P2284 T1/J1 Interrupt Module Indication 0 (040H, 140H, 240H, 340H) Bit No Bit Name IBCD RBOC Type R R Default 0 0 IBCD interrupt is generated in the Inband Loopback Code Detector function block Interrupt is generated in the Inband Loopback Code Detector function block. RBOC interrupt is generated in the Bit-Oriented Message Receiver function block. ...
Page 154
... IDT82P2284 T1/J1 Interrupt Module Indication 1 (041H, 141H, 241H, 341H) Bit No Bit Name THDLC3 THDLC2 Type R R Default 0 0 THDLC3 interrupt is generated in the HDLC Transmitter #3 function block Interrupt is generated in the HDLC Transmitter #3 function block. THDLC2 interrupt is generated in the HDLC Transmitter #2 function block. ...
Page 155
... IDT82P2284 T1/J1 TBIF Option Register (042H, 142H, 242H, 342H) Bit No Bit Name Type Reserved Default FBITGAP: This bit is valid in Transmit Clock Master mode The F-bit is not gapped The F-bit is gapped (no clock signal during the F-bit). DE: This bit selects the active edge of TSCKn to sample the data on TSDn and TSIGn and the active edge of MTSCK to sample the data on MTSDA (MTSDB) and MTSIGA (MTSIGB) ...
Page 156
... IDT82P2284 T1/J1 TBIF Operating Mode (043H, 143H, 243H, 343H) Bit No Bit Name Type Default MAP[1:0]: In Transmit Clock Slave mode and Transmit Multiplexed mode, these 2 bits select the T1/ format mapping schemes. MAP[1:0] Note: * These 2 bits can not be set to ‘00’ in the Transmit Multiplexed mode. ...
Page 157
... IDT82P2284 T1/J1 TBIF TS Offset (044H, 144H, 244H, 344H) Bit No Bit Name TSOFF6 Type Reserved R/W Default 0 TSOFF[6:0]: These bits give a binary number to define the channel offset. The channel offset is between the framing pulse on the TSFSn/MTSFS pin and the start of the corresponding frame input on the TSDn/MTSDA(MTSDB) pin. The signaling bits on the TSIGn/MTSIGA(MTSIGB) pin are always per- channel aligned with the data on the TSDn/MTSDA(MTSDB) pin. In Non-multiplexed mode, the channel offset can be configured from channels (0 & ...
Page 158
... IDT82P2284 T1/J1 RBIF Option Register (046H, 146H, 246H, 346H) Bit No Bit Name Type Reserved Default FBITGAP: This bit is valid in Receive Clock Master mode The F-bit is not gapped The F-bit is gapped (no clock signal during the F-bit). DE: This bit selects the active edge of RSCKn to update the data on RSDn and RSIGn and the active edge of MRSCK to update the data on MRSDA (MRSDB) and MRSIGA (MRSIGB) ...
Page 159
... IDT82P2284 T1/J1 RBIF Mode (047H, 147H, 247H, 347H) Bit No Bit Name Type Default MAP[1:0]: In Receive Clock Slave mode and Receive Multiplexed mode, these 2 bits select the T1/ format mapping schemes. MAP[1:0] Note: * These 2 bits can not be set to ‘00’ in the Receive Multiplexed mode. ...
Page 160
... IDT82P2284 T1/J1 RBIF Frame Pulse (048H, 148H, 248H, 348H) Bit No Bit Name Type Reserved Default FSINV The receive framing pulse RSFSn is active high The receive framing pulse RSFSn is active low. In Receive Multiplexed mode, this bit of the four links should be set to the same value. ...
Page 161
... IDT82P2284 T1/J1 RBIF TS Offset (049H, 149H, 249H, 349H) Bit No Bit Name TSOFF6 Type Reserved R/W Default 0 TSOFF[6:0]: These bits give a binary number to define the channel offset. The channel offset is between the framing pulse on the RSFSn/MRSFS pin and the start of the corresponding frame output on the RSDn/MRSDA(MRSDB) pin. The signaling bits on the RSIGn/MRSIGA(MRSIGB) pin are always per- channel aligned with the data on the RSDn/MRSDA(MRSDB) pin. In Non-multiplexed mode, the channel offset can be configured from channels (0 & ...
Page 162
... IDT82P2284 T1/J1 RTSFS Change Indication (04BH, 14BH, 24BH, 34BH) Bit No Bit Name Type Default RCOFAI: This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode The interval of the pulses on the RSFSn/MRSFS pin is an integer multiple of 125 µ The interval of the pulses on the RSFSn/MRSFS pin is not an integer multiple of 125 µs. ...
Page 163
... IDT82P2284 T1/J1 FRMR Mode 0 (04DH, 14DH, 24DH, 34DH) Bit No Bit Name Type Default UNFM The data stream is received in framed mode and is processed by the Frame Processor The data stream is received in unframed mode and the Frame Processor is bypassed. REFCRCE: In ESF format Disable from re-searching for synchronization when the Excessive CRC-6 Error occurs. ...
Page 164
... IDT82P2284 T1/J1 FRMR Mode 1 (04EH, 14EH, 24EH, 34EH) Bit No Bit Name Type Default DDSC: This bit selects the synchronization criteria format correct DDS pattern is received before the first F-bit of a single correct Frame Alignment Pattern and there is no mimic pattern, the T1 DM synchronization is acquired ...
Page 165
... IDT82P2284 T1/J1 FRMR Status (04FH, 14FH, 24FH, 34FH) Bit No Bit Name Type Default OOFV The SF/ESF/T1 DM/SLC-96 frame is in synchronization The frame is out of synchronization. T1/J1 FRMR Interrupt Control 0 (050H, 150H, 250H, 350H) Bit No Bit Name Type Default OOFE Disable the interrupt on the INT pin when the OOFI bit (b0, T1/J1-052H,...) is ‘1’. ...
Page 166
... IDT82P2284 T1/J1 FRMR Interrupt Control 1 (051H, 151H, 251H, 351H) Bit No Bit Name Type Reserved Default RMFBE Disable the interrupt on the INT pin when the RMFBI bit (b4, T1/J1-053H,...) is ‘1’ Enable the interrupt on the INT pin when the RMFBI bit (b4, T1/J1-053H,...) is ‘1’. ...
Page 167
... IDT82P2284 T1/J1 FRMR Interrupt Indication 0 (052H, 152H, 252H, 352H) Bit No Bit Name Type Reserved Default EXCRCERI: In ESF format, once the accumulated CRC-6 errors exceed 319 (>319 second fixed window, an excessive CRC-6 error event is generated = 0: No Excessive CRC-6 Error event is detected. ...
Page 168
... IDT82P2284 T1/J1 FRMR Interrupt Indication 1 (053H, 153H, 253H, 353H) Bit No Bit Name Type Reserved Default RMFBI The received bit is not the first bit of each SF/ESF/T1 DM/SLC-96 frame The first bit of each SF/ESF/T1 DM/SLC-96 frame is received. This bit will be cleared if a ’1’ is written to it. This bit can not be updated during out of synchronization state. ...
Page 169
... IDT82P2284 COFAI The F bit position is not changed The new-found F bit position differs from the previous one. This bit will be cleared if a ’1’ is written to it. T1/J1 RDL0 (056H, 156H, 256H, 356H) Bit No Bit Name C8 C7 Type R R Default 0 0 C[8:1]: In SLC-96 format, these bits together with the C[11:9] bits reflect the content in the Concentrator bits. The C[1] bit is the LSB. ...
Page 170
... IDT82P2284 T1/J1 RDL2 (058H, 158H, 258H, 358H) Bit No Bit Name Type Reserved Default S[4:1]: In SLC-96 format, these bits reflect the content in the Switch bits. The S[1] bit is the LSB. In de-bounce condition, these bits are updated if the received Switch bits are the same for 2 consecutive SLC-96 frames; otherwise they are updated every SLC-96 frame ...
Page 171
... IDT82P2284 T1/J1 DLB Interrupt Control (05CH, 15CH, 25CH, 35CH) Bit No Bit Name Type Reserved Default SCDEB Disable the de-bounce function of the overhead extraction Enable the de-dounce function of the overhead extraction. SCAE Disable the interrupt on the INT pin when the SCAI bit (b3, T1/J1-05DH,...) is ‘1’. ...
Page 172
... IDT82P2284 T1/J1 DLB Interrupt Indication (05DH, 15DH, 25DH, 35DH) Bit No Bit Name Type Default SCAI The value in the A[2:1] bits is not changed The value in the A[2:1] bits is changed. SCSI The value in the S[4:1] bits is not changed The value in the S[4:1] bits is changed. SCMI The value in the M[3:1] bits is not changed. ...
Page 173
... IDT82P2284 T1/J1 Mode (062H, 162H, 262H, 362H) Bit No Bit Name Type Default FDLBYP: In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’ Enable the DL bit position to be replaced by the Bit-Oriented Code, the Automatic Performance Report Message, the HDLC data or the idle code (‘ ...
Page 174
... IDT82P2284 T1/J1 XDL0 (065H, 165H, 265H, 365H) Bit No Bit Name C8 C7 Type R R Default 0 0 C[8:1]: These bits, together with the C[11:9] bits (b2~0, T1/J1-066H,...), are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDL- BYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain the data to replace the Concentrator (C) bit. The C[1] is the LSB and it is transmitted first. ...
Page 175
... IDT82P2284 T1/J1 XDL2 (067H, 167H, 267H, 367H) Bit No Bit Name Type Reserved Default S[4:1]: These bits are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain the data to replace the Switch (S) bit. The S[1] is transmitted first. ...
Page 176
... IDT82P2284 T1/J1 FGEN Maintenance 1 (06CH, 16CH, 26CH, 36CH) Bit No Bit Name Type Default MIMICEN: This bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’ Disable the mimic pattern insertion The mimic pattern is inserted into the bit right after each F-bit. The content of the mimic pattern is the same as the F-bit. ...
Page 177
... IDT82P2284 T1/J1 FGEN Interrupt Control (06DH, 16DH, 26DH, 36DH) Bit No Bit Name Type Default MFE Disable the interrupt on the INT pin when the MFI bit (b1, T1/J1-06EH,...) is ‘1’ Enable the interrupt on the INT pin when the MFI bit (b1, T1/J1-06EH,...) is ‘1’. ...
Page 178
... IDT82P2284 T1/J1 Error Insertion (06FH, 16FH, 26FH, 36FH) Bit No Bit Name Type Default DDSINV: This bit is valid format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’. A transition from ‘0’ to ‘1’ on this bit wil invert one 6-bit DDS pattern. This bit is cleared when the inversion is completed. ...
Page 179
... IDT82P2284 T1/J1 Transmit Timing Option (070H, 170H, 270H, 370H) Bit No Bit Name Type Default XTS: In Transmit Clock Master mode The source of the transmit clock is selected from the clock generated by the internal clock generator (1.544 MHz The source of the transmit clock is selected from the recovered clock from the line side. ...
Page 180
... IDT82P2284 T1/J1 PRGD Status/Error Control (072H, 172H, 272H, 372H) Bit No Bit Name Type Default BERE Disable the interrupt on the INT pin when the BERI bit (b3, T1/J1-073H,...) is ‘1’ Enable the interrupt on the INT pin when the BERI bit (b3, T1/J1-073H,...) is ‘1’. ...
Page 181
... IDT82P2284 T1/J1 XIBC Control (074H, 174H, 274H, 374H) Bit No Bit Name Type Default IBCDEN Disable transmitting the inband loopback code Enable transmitting the inband loopback code. IBCDUNFM The inband loopback code is transmitted in framed mode, that is, the bits in all 24 channels are overwritten with the inband loopback code and the F-bit is not changed ...
Page 182
... IDT82P2284 T1/J1 IBCD Detector Configuration (076H, 176H, 276H, 376H) Bit No Bit Name Type Reserved Default IBCDIDLE The F-bit is compared with the target activate/deactivate inband loopback code, but the result of the F-bit comparison is discarded The F-bit is skipped in the comparison process. DSEL[1:0]: These two bits define the length of the target deactivate inband loopback code, meanwhile, they define the valid code in the DACT[7:0] bits (b7~0, T1/J1-079H, ...
Page 183
... IDT82P2284 T1/J1 IBCD Detector Status (077H, 177H, 277H, 377H) Bit No Bit Name Type Default LBA The activate code is loss. That is, more than 600 bits are not matched with the target activate inband loopback code in a 39.8ms fixed period The activate code is detected. That is, in more than 126 consecutive 39.8ms fixed periods, the target activate inband loopback code is matched with less than 600 bit errors in each 39 ...
Page 184
... IDT82P2284 T1/J1 IBCD Interrupt Control (07AH, 17AH, 27AH, 37AH) Bit No Bit Name Type Default LBAE Disable the interrupt on the INT pin when the LBAI bit (b1, T1/J1-07BH,...) is ‘1’ Enable the interrupt on the INT pin when the LBAI bit (b1, T1/J1-07BH,...) is ‘1’. ...
Page 185
... IDT82P2284 T1/J1 ELST Configuration (07CH, 17CH, 27CH, 37CH) Bit No Bit Name Type Default TRKEN: In Receive Clock Slave mode and Receive Multiplexed mode out of synchronization, the trunk code programmed in the TRKCODE[7:0] bits (b7~0, T1/J1-07EH,...) can be set to replace the data or not Disable the replacement. ...
Page 186
... IDT82P2284 T1/J1 APRM Control (07FH, 17FH, 27FH, 37FH) Bit No Bit Name Type Reserved Default LBBIT: This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in the LB bit position of the APRM. U2BIT: This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in the U2 bit position of the APRM ...
Page 187
... IDT82P2284 T1/J1 XBOC Code (080H, 180H, 280H, 380H) Bit No Bit Name Type Reserved Default XBOC[5:0]: These bits are only valid in the ESF format. When the XBOC[5:0] bits are written with any 6-bit code other than the ‘111111’, the code will be transmitted as the Bit Oriented Message (BOM). ...
Page 188
... IDT82P2284 T1/J1 BOC Interrupt Indication (082H, 182H, 282H, 382H) Bit No Bit Name Type Default BOCI The BOC[5:0] bits (b5~0, T1/J1-083H,...) are not updated The BOC[5:0] bits (b5~0, T1/J1-083H,...) are updated. This bit will be cleared if a ’1’ is written to it. T1/J1 RBOC Code (083H, 183H, 283H, 383H) Bit No ...
Page 189
... IDT82P2284 T1/J1 THDLC Enable Control (084H, 184H, 284H, 384H) Bit No Bit Name Type Default TDLEN3 All the functions of the HDLC Transmitter #3 is disabled All the functions of the HDLC Transmitter #3 is enabled. TDLEN2 All the functions of the HDLC Transmitter #2 is disabled All the functions of the HDLC Transmitter #2 is enabled. ...
Page 190
... IDT82P2284 T1/J1 THDLC2 Assignment (086H, 186H, 286H, 386H) Bit No Bit Name EVEN Type Reserved R/W Default 0 T1/J1 THDLC3 Assignment (087H, 187H, 287H, 387H) Bit No Bit Name EVEN Type Reserved R/W Default 0 The function of the above two sets of registers are the same. However, they correspond to different THDLC. ...
Page 191
... IDT82P2284 T1/J1 THDLC2 Bit Select (089H, 189H, 289H, 389H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 T1/J1 THDLC3 Bit Select (08AH, 18AH, 28AH, 38AH) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 The function of the above two sets of registers are the same. However, they correspond to different THDLC. ...
Page 192
... IDT82P2284 T1/J1 RHDLC Enable Control (08BH, 18BH, 28BH, 38BH) Bit No Bit Name Type Default RDLEN3 All the functions of the HDLC Receiver #3 is disabled All the functions of the HDLC Receiver #3 is enabled. RDLEN2 All the functions of the HDLC Receiver #2 is disabled All the functions of the HDLC Receiver #2 is enabled. ...
Page 193
... IDT82P2284 T1/J1 RHDLC2 Assignment (08DH, 18DH, 28DH, 38DH) Bit No Bit Name EVEN Type Reserved R/W Default 0 T1/J1 RHDLC3 Assignment (08EH, 18EH, 28EH, 38EH) Bit No Bit Name EVEN Type Reserved R/W Default 0 The function of the above two sets of registers are the same. However, they correspond to different RHDLC. ...
Page 194
... IDT82P2284 T1/J1 RHDLC2 Bit Select (090H, 190H, 290H, 390H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 T1/J1 RHDLC3 Bit Select (091H, 191H, 291H, 391H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 The function of the above two sets of registers are the same. However, they correspond to different RHDLC. ...
Page 195
... IDT82P2284 T1/J1 RHDLC1 Control Register (092H, 192H, 292H, 392H) Bit No Bit Name Type Reserved Default T1/J1 RHDLC2 Control Register (093H, 193H, 293H, 393H) Bit No Bit Name Type Reserved Default T1/J1 RHDLC3 Control Register (094H, 194H, 294H, 394H) Bit No Bit Name Type ...
Page 196
... IDT82P2284 RRST: A transition from ‘0’ to ‘1’ on this bit resets the corresponding HDLC Receiver. The reset will clear the FIFO, the PACK bit (b0, T1/J1-095H,... / 096H,... / 097H,...) and the EMP bit (b1, T1/J1-095H,... / 096H,... / 097H,...). T1/J1 RHDLC1 RFIFO Access Status (095H, 195H, 295H, 395H) Bit No ...
Page 197
... IDT82P2284 T1/J1 RHDLC1 Data (098H, 198H, 298H, 398H) Bit No Bit Name DAT7 DAT6 Type R R Default 0 0 T1/J1 RHDLC2 Data (099H, 199H, 299H, 399H) Bit No Bit Name DAT7 DAT6 Type R R Default 0 0 T1/J1 RHDLC3 Data (09AH, 19AH, 29AH, 39AH) Bit No. ...
Page 198
... IDT82P2284 T1/J1 RHDLC1 Interrupt Control (09BH, 19BH, 29BH, 39BH) Bit No Bit Name Type Default T1/J1 RHDLC2 Interrupt Control (09CH, 19CH, 29CH, 39CH) Bit No Bit Name Type Default T1/J1 RHDLC3 Interrupt Control (09DH, 19DH, 29DH, 39DH) Bit No Bit Name Type Default The function of the above three sets of registers are the same. However, they correspond to different RHDLC. ...
Page 199
... IDT82P2284 T1/J1 RHDLC1 Interrupt Indication (09EH, 19EH, 29EH, 39EH) Bit No Bit Name Type Default T1/J1 RHDLC2 Interrupt Indication (09FH, 19FH, 29FH, 39FH) Bit No Bit Name Type Default T1/J1 RHDLC3 Interrupt Indication (0A0H, 1A0H, 2A0H, 3A0H) Bit No Bit Name Type Default The function of the above three sets of registers are the same. However, they correspond to different RHDLC. ...
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... IDT82P2284 T1/J1 RHDLC1 High Address (0A1H, 1A1H, 2A1H, 3A1H) Bit No Bit Name HA7 HA6 Type R/W R/W Default 0 0 T1/J1 RHDLC2 High Address (0A2H, 1A2H, 2A2H, 3A2H) Bit No Bit Name HA7 HA6 Type R/W R/W Default 0 0 T1/J1 RHDLC3 High Address (0A3H, 1A3H, 2A3H, 3A3H) Bit No. ...