IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 68

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
pin and the framing pulse on the RSFSn pin to output the data on the
RSDn pin are provided by the system side. When the RSLVCK bit is set
to ‘0’, each link uses its own RSCKn and RSFSn; when the RSLVCK bit
is set to ‘1’ and all four links are in the Receive Clock Slave mode, the
four links use the RSCK[1] and RSFS[1] to output the data. The signal-
ing bits on the RSIGn pin are per-channel aligned with the data on the
RSDn pin.
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the RSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If all four links use the
RSCK[1] and RSFS[1] to output the data, the CMS bit of the four links
should be set to the same value. If the speed of the RSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to update the data on the
RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled
on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125 µs, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.3
four links should be mapped to 2.048 Mb/s format first, the 3 kinds of
schemes should be selected by the MAP[1:0] bits. The mapping per
G.802, per One Filler Every Four CHs and per Continuous CHs are the
same as the description in Chapter 3.17.1.2 Receive Clock Slave Mode.
put the data from all four links. The data of Link 1 to Link 4 is byte-inter-
Functional Description
1.544
2.048
Mb/s
Mb/s
In the Receive Clock Slave mode, the timing signal on the RSCKn
In the Receive Clock Slave mode, the data on the system interface
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
In the Receive Multiplexed mode, since the received data from the
In the Receive Multiplexed mode, a multiplexed bus is used to out-
filler
Receive Multiplexed Mode
TS0
the 8th bit
F
CH1
TS1
Figure 19. T1/J1 To E1 Format Mapping - Continuous Channels Mode
CH2
TS2
TS3
CH3
TS23
CH23
TS24
57
CH24
leaved output on the multiplexed bus 1. When the data from the four
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the channel offset. The data from different links on
one multiplexed bus must be shifted at a different channel offset to avoid
data mixing.
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to all four links. The signaling bits on the MRSIGA
(MRSIGB) pin are per-channel aligned with the corresponding data on
the MRSDA (MRSDB) pin.
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSDA (MRSDB)
and MRSIGA (MRSIGB) is determined by the DE bit. The FE bit and the
DE bit of the four links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MRSFS is
ahead. The MRSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MRSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) pins. The pulse on the MRSFS pin is always sam-
pled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
four links should be set to the same value. If the pulse on the MRSFS
pin is not an integer multiple of 125 µs, this detection will be indicated by
the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be
reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.4
modes. The offset is between the framing pulse on RSFSn/MRSFS pin
and the start of the corresponding frame output on the RSDn/
MRSDA(MRSDB)
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TS25~TS31
In the Receive Multiplexed mode, the timing signal on the MRSCK
In the Receive Multiplexed mode, the data on the system interface
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
Bit offset and channel offset are both supported in all the operating
filler
F
CH1
Offset
filler
TS0
pin.
the 8th bit
CH2
The
TS1
signaling
TS2
bits
CH24
on
March 22, 2004
F CH1
the
TS24
RSIGn/