IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 56

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
3.11
selected position and processes the data according to the selected
mode.
3.11.1
#2 & #3) per link are provided for HDLC extraction from the received
data stream. In T1/J1 mode SF & SLC-96 formats, two HDLC Receivers
(#2 & #3) per link are provided for HDLC extraction. In E1 mode, three
HDLC Receivers (#1, #2 & #3) per link are provided for HDLC extraction.
Except in T1/J1 mode ESF & T1 DM formats, the HDLC channel of
Table 29: Related Bit / Register In Chapter 3.11.1
3.11.2
HDLC Receiver. The two modes are: HDLC mode (per Q.921) and SS7
mode (per Q.703).
3.11.2.1
parts as shown in Figure 12. Each HDLC packet starts with a 7E (Hex)
discarded, the data stream between the opening flag and the FCS is
divided into blocks. Each block (except the last block) has 32 bytes. The
Functional Description
BITEN[7:0]
The HDLC Receiver extracts the HDLC/SS7 data stream from the
In T1/J1 mode ESF & T1 DM formats, three HDLC Receivers (#1,
Two modes are selected by the RHDLCM bit in the corresponding
The structure of a standard HDLC packet consists of the following
After the stuffed zero (the zero following five consecutive ’One’s) is
RDLEN3
RDLEN2
RDLEN1
'01111110'
TS[4:0]
EVEN
one byte
ODD
Bit
Flag
HDLC RECEIVER
HDLC CHANNEL CONFIGURATION
TWO HDLC MODES
HDLC Mode
RHDLC1 Assignment (E1 only) / RHDLC2 Assignment /
RHDLC1 Bit Select (E1 only) / RHDLC2 Bit Select /
two bytes
FCS
RHDLC Enable Control
RHDLC3 Assignment
RHDLC3 Bit Select
Register
Figure 12. Standard HDLC Packet
Information
n bytes
b7
45
HDLC #1 is fixed in the DL bit (in ESF format) and D bit in CH24 (in T1
DM format) respectively (refer to Table 13 & Table 14), the other HDLC
channels are configured as follows:
odd frames;
assigned frame;
timeslot.
the corresponding RDLEN bit is set to ‘1’.
opening flag and ends with the same flag. The closing flag may also
serve as the opening flag of the next HDLC packet. Following the open-
ing flag, two-byte address is compared if the address comparison mode
is selected. Before the closing flag, two bytes of CRC-CCITT frame
check sequences (FCS) are provided to check all the HDLC packet
(excluding the opening flag and closing flag).
block will be pushed into a FIFO with one-byte overhead ahead until any
of the following invalid packet conditions occurs:
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
08C, 18C, 28C, 38C (E1 only) / 08D, 18D, 28D, 38D / 08E, 18E, 28E,
08F, 18F, 28F, 38F (E1 only) / 090, 190, 290, 390 / 091, 191, 291,
1. Set the EVEN bit and/or the ODD bit to select the even and/or
2. Set the TS[4:0] bits to define the channel/timeslot of the
3. Set the BITEN[7:0] bits to select the bits of the assigned channel/
Then all the functions of the HDLC Receiver will be enabled only if
- A packet with error FCS;
one byte
Control
one byte
low byte
address
b0
(optional)
08B, 18B, 28B, 38B
Address
b7
Address (Hex)
high byte
one byte
address
38E
391
'01111110'
one byte
Flag
March 22, 2004
C/R
b0