IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 103

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
3.27.2
2, Remote Loopback and Analog Loopback are all supported in the
IDT82P2284. Their routes are shown in the Functional Block Diagram.
3.27.2.1
System Interface and the Transmit System Interface are in different
Non-multiplexed operating modes (one in Clock Master mode and the
other in Clock Slave mode). However, in T1/J1 mode, when either the
receive path or the transmit path is in T1/J1 mode E1 rate, the System
Loopback is not supported.
be divided into System Remote Loopback and System Local Loopback.
When the data and signaling bits from the transmit path are looped to
the receive path, it is System Remote Loopback. When the data and sig-
naling bits from the receive path are looped to the transmit path, it is
System Local Loopback.
3.27.2.1.1
mented. The data and signaling bits to be transmitted on the TSDn and
TSIGn pins are internally looped to the RSDn and RSIGn pins. When
the receive path is in Receive Clock Master mode and the transmit path
is in Transmit Clock Slave mode, the clock signal and the framing pulse
from the system side on the TSCKn and TSFSn pins are looped to the
RSCKn and RSFSn pins respectively. When the transmit path is in
Transmit Clock Master mode and the receive path is in Receive Clock
Slave mode, the clock signal and the framing pulse from the system side
on the RSCKn and RSFSn pins are looped to the TSCKn and TSFSn
pins respectively.
ted is still output to the line side, while the data stream received from the
line side is replaced by the System Remote Loopback data.
3.27.2.1.2
mented. The received data and signaling bits to be output on the RSDn
and RSIGn pins are internally looped to the TSDn and TSIGn pins.
When the receive path is in Receive Clock Master mode and the trans-
mit path is in Transmit Clock Slave mode, the recovered clock signal and
framing pulse on the RSCKn and RSFSn pins are looped to the TSCKn
and TSFSn pins respectively. When the transmit path is in Transmit
Clock Master mode and the receive path is in Receive Clock Slave
mode, the TSCKn and TSFSn pins are looped to the RSCKn and
RSFSn pins respectively.
the line side is still output to the system through the RSDn and RSIGn
pins, while the data stream to be transmitted through the TSDn and
TSIGn pins are replaced by the System Local Loopback data.
System Loopback, Payload Loopback, Local Digital Loopback 1 &
The System Loopback can only be implemented when the Receive
Distinguished by the loopback direction, the System Loopback can
Enabled by the SRLP bit, the System Remote Loopback is imple-
In System Remote Loopback mode, the data stream to be transmit-
Enabled by the SLLP bit, the System Local Loopback is imple-
In System Local Loopback mode, the data stream received from
LOOPBACK
System Loopback
System Remote Loopback
System Local Loopback
92
3.27.2.2
Payload Loopback can be implemented. The received data output from
the Elastic Store Buffer is internally looped to the Transmit Payload Con-
trol.
system side, while the data to be transmitted from the system side is
replaced by the Payload Loopback data.
3.27.2.3
mented. The data stream output from the Transmit Buffer is internally
looped to the Frame Processor.
ted is still output to the line side, while the data stream received from the
line side is replaced by the Local Digital Loopback 1 data.
3.27.2.4
data stream output from the optional Receive Jitter Attenuator is inter-
nally looped to the optional Transmit Jitter Attenuator.
side is still output to the system, while the data stream to be transmitted
is replaced by the Remote Loopback data.
3.27.2.5
mented. The data stream output from the optional Transmit Jitter Attenu-
ator is internally looped to the Optional Receive Jitter Attenuator.
ted is still output to the line side, while the data stream received from the
line side is replaced by the Local Digital Loopback 2 data.
3.27.2.6
data stream to be transmitted on the TTIPn/TRINGn pins is internally
looped to the RTIPn/RRINGn pins.
output to the line side, while the data stream received from the line side
is replaced by the Analog Loopback data.
3.27.3
three links are in normal operation and the Link 1 is configured to moni-
tor the receive path or transmit path of any of the remaining links.
which direction (receive/transmit) and link is monitored are both deter-
mined by the MON[3:0] bits.
shown in Figure 35. The data stream of Link 1 is received from the
selected path of any of the remaining links, then processed as normal.
The operation of the monitored link is not effected.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
By programming the GSUBST[2:0] bits or the SUBST[2:0] bits, the
In Payload Loopback mode, the received data is still output to the
Enabled by the DLLP bit, the Local Digital Loopback 1 is imple-
In Local Digital Loopback 1 mode, the data stream to be transmit-
Enabled by the RLP bit, the Remote Loopback is implemented. The
In Remote Loopback mode, the data stream received from the line
Enabled by the DLP bit, the Local Digital Loopback 2 is imple-
In Local Digital Loopback 2 mode, the data stream to be transmit-
Enabled by the ALP bit, the Analog Loopback is implemented. The
In Analog Loopback mode, the data stream to be transmitted is still
When the G.772 Non-Intrusive Monitoring is implemented, only
Whether the G.772 Non-Intrusive Monitoring is implemented and
The G.772 Non-Intrusive Monitoring meets the ITU-T G.772. It is
G.772 NON-INTRUSIVE MONITORING
Payload Loopback
Local Digital Loopback 1
Remote Loopback
Local Digital Loopback 2
Analog Loopback
March 22, 2004