IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 51
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IDT82P2284
Manufacturer Part Number
IDT82P2284
Description
4 Channel T1/J1/E1 Transceiver
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT82P2284.pdf
(384 pages)
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IDT82P2284
3.9.2
formance monitoring. The overflow of each counter is reflected by an
Overflow Indication Bit, and can trigger an interrupt if the corresponding
Overflow Interrupt Enable Bit is set. This is shown in Table 24.
accessed through other direct registers. At one time, only one internal
counter can be accessed. Users should use the LINKSEL[1:0] bits to
select the Link, then use the ADDR[3:0] bits to select one internal
counter. The content of the selected counter is transferred to the
DATA[7:0] bits in the following two ways:
Functional Description
Table 24: Monitored Events In E1 Mode
Bipolar Violation (BPV) Error (in AMI decoding) or HDB3 Code Violation (CV) Error (in HDB3 decoding)
FAS/NFAS Bit/Pattern Error
CRC-4 Error
Far End Block Error
The the new-found Basic frame alignment pattern position differs from the previous one
Out of Basic frame synchronization
PRGD Bit Error
NT FEBE Error
NT CRC Error
Several internal counters are used to count different events for per-
These internal counters are indirect registers, and can only be
E1 MODE
Event
40
transfers its content to the DATA[7:0] bits every one second automati-
cally;
time, when there is a transition from ‘0’ to ‘1’ on the UPDAT bit, the
selected counter will transfer its content to the DATA[7:0] bits.
DATA[7:0] bits, all counters belong to the selected Link will be cleared to
‘0’ as a group and start a new round counting automatically. No error
event is lost during updating.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
1. Auto-Report: When the AUTOUP bit is ‘1’, the selected counter
2. Manual-Report: No matter the AUTOUPD bit is ‘1’ or ‘0’, at any
After the content in the selected counter is transferred to the
PRGD[15:0]
TCRCE[9:0]
TFEBE[9:0]
CRCE[9:0]
COFA[2:0]
FEBE[9:0]
LCV[15:0]
FER[11:0]
OOF[4:0]
Counter
Overflow Interrupt
Indication Bit
TFEBEOVI
PRGDOVI
COFAOVI
TCRCOVI
FEBEOVI
CRCOVI
OOFOVI
FEROVI
LCVOVI
Overflow Interrupt
March 22, 2004
TFEBEOVE
PRGDOVE
Enable Bit
COFAOVE
TCRCOVE
FEBEOVE
OOFOVE
CRCOVE
LCVOVE
FEROVE
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