IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 49

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
3.9
3.9.1
formance monitoring. For different framing format, the counters are used
differently. The overflow of each counter is reflected by an Overflow Indi-
cation Bit, and can trigger an interrupt if the corresponding Overflow
Interrupt Enable Bit is set. This is shown in Table 22.
accessed through other direct registers. At one time, only one internal
counter can be accessed. Users should use the LINKSEL[1:0] bits to
select the Link, then use the ADDR[3:0] bits to select one internal
Table 22: Monitored Events In T1/J1 Mode
Functional Description
(T1 only)
(T1 only)
Format
SLC-96
T1 DM
ESF
SF
Several internal counters are used to count different events for per-
These internal counters are indirect registers, and can only be
PERFORMANCE MONITOR
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
F Bit Error
The new-found F bit position differs from the previous one
Out of SF synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
Frame Alignment Bit Error
CRC-6 Error
The new-found F bit position differs from the previous one
Out of ESF synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
F Bit Error
DDS Pattern Error
The new-found F bit position differs from the previous one
Out of T1 DM synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
F Bit Error
The new-found F bit position differs from the previous one
Out of SLC-96 synchronization
PRGD Bit Error
T1/J1 MODE
Event
PRGD[15:0]
PRGD[15:0]
PRGD[15:0]
PRGD[15:0]
38
CRCE[9:0]
COFA[2:0]
COFA[2:0]
DDSE[9:0]
COFA[2:0]
COFA[2:0]
LCV[15:0]
FER[11:0]
LCV[15:0]
FER[11:0]
LCV[15:0]
FER[11:0]
LCV[15:0]
FER[11:0]
OOF[4:0]
OOF[4:0]
OOF[4:0]
OOF[4:0]
Counter
counter. The content of the selected counter is transferred to the
DATA[7:0] bits in the following two ways:
transfers its content to the DATA[7:0] bits every one second automati-
cally;
time, when there is a transition from ‘0’ to ‘1’ on the UPDAT bit, the
selected counter will transfer its content to the DATA[7:0] bits.
DATA[7:0] bits, all counters belong to the selected Link will be cleared to
‘0’ as a group and start a new round counting automatically. No error
event is lost during updating.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
1. Auto-Report: When the AUTOUP bit is ‘1’, the selected counter
2. Manual-Report: No matter the AUTOUPD bit is ‘1’ or ‘0’, at any
After the content in the selected counter is transferred to the
Overflow Interrupt Indication Bit Overflow Interrupt Enable Bit
PRGDOVI
PRGDOVI
PRGDOVI
PRGDOVI
COFAOVI
COFAOVI
COFAOVI
COFAOVI
OOFOVI
CRCOVI
OOFOVI
DDSOVI
OOFOVI
OOFOVI
LCVOVI
FEROVI
LCVOVI
FEROVI
LCVOVI
FEROVI
LCVOVI
FEROVI
PRGDOVE
PRGDOVE
PRGDOVE
PRGDOVE
COFAOVE
COFAOVE
COFAOVE
COFAOVE
OOFOVE
CRCOVE
OOFOVE
OOFOVE
OOFOVE
FEROVE
FEROVE
FEROVE
DDSOVE
FEROVE
LCVOVE
LCVOVE
LCVOVE
LCVOVE
March 22, 2004