MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 103
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MT90221
Manufacturer Part Number
MT90221
Description
Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90221.pdf
(115 pages)
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MT90221
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
94
AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle
1
2
3
4
5
UP_AD[9:0]
UP_D[7:0]
UP_R/W* set-up time to UP_CS*
falling edge
Address and Data set up before
rising edge of UP_CS*
UP_AD and Data hold time after
UP_CS rising edge
UP_R/W low after rising edge or
UP_CS
UP_CS* high before next UP_CS
low
UP_R/W
UP_OE
UP_CS
Characteristics
t
ws
Figure 33 - CPU Interface Motorola Timing - Write Access
Sym
t
t
t
t
ADH
CSH
t
WS
WH
SU
(see Note 1)
Address Valid
Data Valid
Min
1
4
0
1
2
t
su
Typ
t
t
wh
adh
Max
system
t
Units
csh
cycle
clock
ns
ns
ns
ns
Test Conditions
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