MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 13

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
Pin Description (continued)
4
34, 35, 36,
205, 206,
207, 2, 3,
9, 10, 11,
188, 189,
190, 191,
192, 195,
196,197
37, 38
4, 5, 6
12, 13
Pin #
202
203
32
30
20
15
17
RxSOC
RxData
RxAddr
TxAddr
RxClav
TxClav
RxEnb
TxEnb
Name
TxClk
RxClk
[4:0]
[7:0]
[4:0]
sr_d
[7:0]
ATM Output Port Signals (UTOPIA Receive Interface) (see Note 1)
I/O
I/O Static Memory Data Bus. Data Bus to exchange data between the MT90221 and
O UTOPIA Transmit Cell Available Indication Signal. For cell-level flow control in a
O UTOPIA Receive Data Bus. Byte-wide data driven from MT90221 to ATM layer
O UTOPIA Receive Start of Cell Signal. Active high asserted by the MT90221 when
O UTOPIA Receive Cell Available Indication Signal. For cell-level flow control in a
I
I
I
I
I
I
Receiver Static Memory Interface Signals (see Note 1)
UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the
MT90221 which synchronizes data transfers on TxData[1:0]. This signal is the
clock of the incoming data. Data is sampled on the rising edge of this signal.
UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM LAYER
device during cycles when TxData contains valid cell data.
MPHY environment, TxClav is an active high tri-stateable signal from the MT90221
to the ATM LAYER device. A polled MT90221 drives TxClav only during each cycle
following one with its address on the TxAddr lines. The polled MT90221 asserts
TxClav high to indicate it can accept the transfer of a complete cell, otherwise it de-
asserts the signal.
Transmit Address.Five bit wide true data driven from the ATM to the PHY layer to
poll and select the appropriate MT90221. TxAddr[4] is the MSB. Each MT90221
keeps its addresses. The value for the Tx and Rx portions of the MT90221 can be
different
device. RxData[1] is the MSB. To support multiple PHY configurations, RxData is
tri-stateable, enabled only in cycles following those with RxEnb asserted.
RxData contains the first valid byte of a cell. To support multiple PHY
configurations, RxSOC is tri-stateable, enabled only in cycles following those with
RxEnb asserted.
UTOPIA Receive Byte Clock
changes after the rising edge of this signal. The RxClk needs to be synchronized
with the system clock.
UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer
device to indicate that RxData[3:0] and RxSOC will be sampled at the end of the
next cycle. In multiple PHY configurations, RxEnb* is used to tri-state RxData and
RxSOC MT90221 outputs. In that case, RxData and RxSOC would be enabled only
in cycles following those with RxEnb asserted.
MPHY environment, RxClav is an active high tri-stateable signal from the MT90221
to ATM LAYER device. A polled MT90221 drives RxClav only during each cycle
following one with its address on the TxAddr lines. The polled MT90221 asserts
RxClav high to indicate it has a complete cell available for transfer to the ATM Layer
device, otherwise it de-asserts the signal. This signal indicates cycles when there is
valid information on RxData / RxSOC.
Receive Address. Five bit wide true data driven from the ATM to PHY layer to
select the appropriate MT90221. RxAddr[4] is the MSB. Each MT90221 keeps its
address. The value for the Tx and Rx portions of the MT90221 can be different.
the external static memory.
.
This signal is the clock of the outgoing data. Data
Description