MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 36

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

or four external REFCK clocks. As there is no PLL
inside the MT90221, the source frequency has to be
a valid ST-BUS Clock signal (i.e., 4.096 MHz). The
TXSYNC signal is generated by the MT90221 and
meets the ST-BUS format. It is not synchronized with
any other RXSYNC or TXSYNC signal.
4.2.3
In PCM Modes 1 and 5, the TXCK clock frequency
can be either 1.544 or 2.048 MHz. In the PCM Mode
1, the TXCK and TXSYNC pins are outputs. In the
PCM Mode 5, the TXCK and TXSYNC pins are
defined as inputs.
4.2.3.1
In this sub-mode, (selected by clearing the bit 4 of
the TX PCM Control Register 1,) the serial PCM
Interface rate is equal to the line bit rate. When
selected to operate in this sub-mode, the interface
clock is 1.544 MHz and the DSTo and DSTi the data
lines transport only 24 time-slots plus the DS1
framing bit for a total of 193 bits per frame.
E1 Time-Slots
Voice/Data Channels
(DSTi/o)
E1 Time-Slots
Voice/Data Channels
(DSTi/o)
Mode 1 and 5: Generic PCM Interface for T1
1.544 MHz Clock
ST-BUS
Bit Cells
(DSTx0-3)
Serial Bit
Stream
TXSYNC
RXSYNC
TXCK
RXCK
Serial Bit
Stream
TXSYNC
RXSYNC
TXCK
RXCK
ST-BUS
Bit Cells
(DSTx0-3)
16
Channel 31 bit 0
Channel 15 bit 0
0
x
x
Figure 11 - PCM Mode 4 and 8: ST-BUS Interface for E1
-
-
Bit Cell
Bit Cell
16
17
Table 10 - Channel Mapping from ST-BUS to E1
1
1
17
18
2
2
18
19
High Impedance
Channel 16 bit 7
High Impedance
3
3
Channel 0 bit 7
Unused or
Unused or
19
20
4
4
20
21
5
5
The frequency value for TXSYNC and RXSYNC is 8
kHz. The frequency for the TXCK and RXCK is 1.544
Mhz.
The edge of the RXCK and TXCK signals used to
sample incoming data and transmit the outgoing data
is fully programmable on a per link basis. This allows
the MT90221 to operate with the majority of available
off-the-shelf T1 framers.
When operating in the generic PCM system Interface
at 1.544 MHz, the MT90221 does not use the first bit
of the PCM frame (i.e., the T1 framing bit) to perform
the G.804 recommended transmission convergence
function (see Figure 12). This frame bit is also
ignored on the receive side. The position of the
frame bit is indicated by the TXSYNC and RXSYNC
signals.
4.2.3.2
In this sub-mode (selected by setting the bit 4 of the
TX PCM Control Register 1) the channel/timeslot
mapping for this mode is similar to the ST-BUS mode
for T1. The same PCM mapping schemes (grouped
21
22
...
...
...
...
...
...
...
...
6
6
22
23
High Impedance
Channel 16 bit 0
High Impedance
7
7
Channel 0 bit 0
Unused or
Unused or
2.048 MHz Clock
23
24
8
8
24
25
9
9
10
10
25
26
Channel 17 bit 7
Channel 1 bit 7
Bit Cell
11
11
26
27
Bit Cell
12
12
27
28
MT90221
13
13
28
29
...
...
...
...
...
...
...
...
14
14
29
30
15
15
30
31
27