MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 54

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

7.2
Tables 23 to 37 describe the Transmit registers.
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Bin):
Bit #
Bit #
Bit #
Bit #
7:4
3:0
7:4
3:0
7:5
4:0
7:4
3:0
4:1
7
6
5
0
TX Registers Description
Type
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
Goes to 0 during initialization and returns to 1 on completion of initialization.
Reserved, write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved, write 0’s for normal operation.
Reserved. Write 0 to initialize the Cell RAM.
TX FIFO Length Link 1.
TX FIFO Length Link 0.
TX FIFO Length Link 3.
TX FIFO Length Link 2.
Write 0 for normal operation.
Write 1000 to load the TX Utopia FIFO level of IMA group 0
Write 1001 to load the TX Utopia FIFO level of IMA group 1.
Write 1010 to load the TX Utopia FIFO level of IMA group 2.
Write 1011 to load the TX Utopia FIFO level of IMA group 3.
Reserved, read 0’s.
Level of selected FIFO.
150
00
14A
33
14B
33
140
1X000000
Used for initialization of the TX Cell RAM (Filler, Idle Cells etc.)
Table 25 - TX FIFO Length Definition Register 1
Table 26 - TX FIFO Length Definition Register 2
Table 24 - TX UTOPIA FIFO Level Register
Table 23 - TX Cell RAM Control Register
Description
Description
Description
Description
MT90221
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