MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 28

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

window’s base address and the new cell at the base
address plus 0x40.
The RX ICP Cell Level FIFO register is used to read
the level of any of the 4 RX ICP Cell buffers. A ’0’ in
this register signifies that no new cell has been
received. A ’2’ indicates the possibility that one or
more cells have been missed (overflow condition).
The cell in the last entry of the circular buffer is the
last cell that was meeting the selection criteria. If the
Cell FIFO level is 2, it is constantly overwritten by
any new valid incoming cell.
The cell that is at the window’s base address when
the level is 0 is never overwritten as it is kept for
reference.
The RX ICP Cell Buffer Increment Read Pointer
register is used to advance the access window by 1
cell at a time. Upon the command, the Buffer level is
decreased by 1. When the level reaches 0, the
window is not advanced anymore.
During the start-up phase, the software can select to
collect all valid ICP cells coming in a RX PCM port
and determine if the parameters are acceptable to
proceed and start-up an IMA group.
In normal IMA operating mode, the software will
select to collect only valid ICP with changes. The
Status and Control Change Indication (SCCI) is
monitored for all valid ICP cells received. If the SCCI
field indicates a change in the ICP cells, they are put
aside for processing by software.
To accelerate the processing of ICP cells that contain
changes, any byte of the last and next processed
ICP cell can be accessed directly. To reduce the total
processing time by the software, only those bytes
that need to be read are accessed. The storage unit
keeps the last read ICP cell and has room for up to
three new ICP cells.
3.3.7
The MT90221 computes the internal RX IMA Data
Cell Rate (IDCR) for each IMA Group. The cell rate
of
programmable period of time. Software must specify
the reference link for the IMA Group in the RX
Reference Link Control register and the period of
integration in the RX IDCR Integration register.
Refer to TX IMA Data Cell Rate in Section 2.4.5.
As an option, the reference link can be extracted
automatically from the received ICP cell. This option
the
Rate Recovery
reference
link
is
integrated
over
a
is selected by bit 4 of the RX Reference Link
Control registers. When this option is enabled, the
RX Reference Link is always updated to reflect the
content of the last valid RXICP cell that was
received.
3.3.8
The received cells are temporarily stored in external
memory buffers until they can be correctly re-ordered
for output. Memory size depends on the number of
links and the maximum delay allowed between the
links.
configurations is listed in Table 4. The memory is
organized in blocks of 64 bytes. Each block can hold
one cell. The following equation can be used to
determine the maximum delay value or the required
RAM size for a determined delay:
To simplify the RAM interface and pin loading, the
MT90221 supports the following six, SRAM Control
register selectable, external memory configurations:
•
•
•
•
•
•
To enable the correct memory access, the Test
Mode Enable register bit 7 has to be set to 1, the
value 0x10 should be written to the RX Delay Link
Number register, the bit 3 of the RX External SRAM
Control register has to be set to 1 and the bit 6 of
Test 2 register has to be set to 1.
3.3.9
When an IMA Group is active, the IMA recombiner
manages the pointers to the external RAM write and
read location for the stored ATM cells. A cell is read
out from the buffer located in the external RAM
Memory Size
Note: Assuming a Guardband of 4 cells
one 32 KByte SRAM device
two 32 KByte SRAM devices
one 128 KByte SRAM device
two 128 KByte SRAM devices
one 512 KBytes SRAM
two 512 KBytes SRAM devices.
(Kbytes)
1024Kb
128Kb
256Kb
512Kb
32Kb
64Kb
The
Cell Buffer/RAM Controller
Cell Sequence Recovery
Table 4 - Differential Delay for Various
MaxDelay
memory
Memory Configuration
=
T1 links
---------------------------- -
RAMsize
140
281
560
requirements
16
34
69
64
Delay (msec)
1
-- - 1CellTime
8
MT90221
E1 links
for
112
225
451
13
27
55
different
19