MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 75
MT90221
Manufacturer Part Number
MT90221
Description
Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90221.pdf
(115 pages)
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MT90221
7.9
Tables 80 to 88 describe the TX/RX and PLL Control registers.
66
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
7:5
3:0
6:5
4
7
4
3
TX/RX and PLL Control Registers Description
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
Unused. Read all 0’s.
TXCK and TXSYNC Direction:
When the bit is 0 (default value)
When the bit is 1
These 4 bits are used to select the source for the TXCK for the link:
The valid combinations are:
0000: RXCK0
0001: RXCK1
0010: RXCK2
0011: RXCK3
1000: REFCK0
1001: REFCK1
1010: REFCK2
1011: REFCK3
PCM port tri-state control. TXCLK, TXSYNC and DSTO outputs are active when the bit is
1. The outputs of the Port is in tri-state if the bit is 0.
00: T1, Generic Mode, 1.544MHz or 2.048 MHz Clk, (Mode 1 or 5)
01: T1, ST-BUS Mode, 4.096MHz Clk, (Mode 2 or 6)
10: E1, Generic Mode, 2.048 MHz clk, (Mode 3 or 7)
11: E1, ST-BUS Mode, 4.096MHz Clk, (Mode 4 or 8)
The direction of the TXCK and TXSYNC signals (i.e.; input or output) is defined using the
TX PCM Link Control register #2 bit 4.
This bit defines the PCM clock rate when one of the 2 T1 generic modes is selected. A 1
signifies that a 2.048 MHz clock is used and a 0 signifies that a 1.544 MHz clock is used.
This bit is valid only for T1 Generic modes (PCM Mode 1 or 5).
This bit defines the position of the PCM channels over the PCM Stream. A value of 1
means that the 24 channels are grouped and transmitted in the first 24 channels on the
PCM stream. A value of 0 corresponds to using 3 channels every 4 channels. This bit is
valid only for T1 type link, in ST-BUS or Generic mode with a TXCK frequency of
2.048MHz. It is not applicable for T1, Generic mode with TXCK frequency of 1.544MHz.
080 - 083
1 reg. per TX link
00
088 - 08B
1 reg. per TX link
00
Mode 1: TXCK and TXSYNC are outputs
Mode 2: TXCK and TXSYNC are inputs
Mode 3: TXCK and TXSYNC are outputs
Mode 4: TXCK and TXSYNC are inputs
Mode 5: TXCK and TXSYNC are inputs
Mode 6: TXCK and TXSYNC are outputs
Mode 7: TXCK and TXSYNC are inputs
Mode 8: TXCK and TXSYNC are outputs
Table 80 - TX PCM Link Control Register Number 2
Table 81 - TX PCM Link Control Register Number 1
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