MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 67

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
58
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access Set Address for an indirect access to write to ICP Cell RAM
Reset Value (Hex):
Bit #
Bit #
Bit #
7-4
7:6
5:4
3:2
1:0
2:0
2:0
3
2
1
0
7
6
5
4
3
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
R
R
R
R
Table 57 - RX ICP Cell Buffer Increment Read Pointer Register
Reserved. Write 0 for normal operation.
A value of 1 will increment the position of the read pointer for the physical link 3. A 0 has
no effect.
A value of 1 will increment the position of the read pointer for the physical link 2. A 0 has
no effect.
A value of 1 will increment the position of the read pointer for the physical link 1. A 0 has
no effect.
A value of 1 will increment the position of the read pointer for the physical link 0. A 0 has
no effect.
Unused. Read all 0’s.
Level of RX ICP Cell FIFO.
FIFO write pointer position
FIFO read pointer position
Select link number for FIFO Status.
0: External SRAM Test Mode is disabled,
1: External SRAM Test Mode is enabled.
Reserved, write 0 for normal operation.
Reserved, write 0 for normal operation.
Reserved, write 0 for normal operation.
Reserved, write 0 for normal operation.
Reserved, write 0’s for normal operation.
1C6
1 reg. for all 4 RX link FIFO
00
1C7
Write to bit 2:0 of this register to select the specific link RX ICP Cell FIFO. The
value is immediately updated for a read
00
1C3
00
Table 58 - RX ICP Cell Level FIFO Status Register
Table 59 - Test Mode Enable Register
Description
Description
Description