MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 37

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
or spaced) are supported. The TXCLK and RXCLK
are 2.048 MHz signal and the TXSYNC and
RXSYNC are a frame pulse of one full bit duration
that occurs at the beginning of the frame. The frame
rate is 8 KHz. The polarity of the TXCK, RXCK,
TXSYNC and RXSYNC and their active edge is
programmable using TX PCM Link Control register
number 1 and RX PCM Link Control register.
4.2.4
The channel/timeslot mapping in this mode is similar
to the ST-BUS mode for E1. The differences are:
•
•
•
•
The edge of the RXCK and TXCK signals that is
used to sample the incoming, and transmit the
outgoing, data is fully programmable on a per link
basis. This allows the MT90221 to operate with the
majority of off-the-shelf E1 framers.
The MT90221 does not use timeslots 0 and 16 to
perform
function (see Figure 13).
4.2.5
The TXSYNC signal is defined as an input in PCM
mode 5 and 7 and is sampled at the bit boundary. A
positive delay of 10 nsec is expected between the
TXCLK signal at the bit boundary and the time the
28
the interface clocks (RXCK and TXCK) operate
at 2.048 MHz only
the synchronization signals (TXSYNC and
RXSYNC) are valid for one clock cycle (488
nsec) during the first bit of the frame
In PCM Mode 3, the TXCK and TXSYNC pins
are defined as outputs.
In PCM Mode 7, the TXCK and TXSYNC are
defined as inputs.
Mode 3 and 7: Generic PCM Interface for E1
TXSYNC Signal in Mode 5 and 7
the
G.804
T1 Frame
Bit Cells
at DSTx0-3
Serial Bit
Stream
TXSYNC
TXCK
RXSYNC
RXCK
transmission
Figure 12 - Mode 1 and 5: Generic PCM Interface for T1
convergence
Bit Cell
bit 193
High Impedance
Unused or
TXSYNC changes
operability
connected to some off-the-shelf framers as the
TXSYNC can be slightly ahead of the TXCLK signal.
In this case, the TXSYNC signal need to be delayed
to ensure proper operation of the TX PCM port.
4.3
In PCM Modes 2, 4, 5 and 7, the TXCK and TXSYNC
are inputs and are generated by external circuitry.
In PCM Modes 1, 3, 6 and 8, the TXCK and TXSYNC
are outputs. TXCK source is software selectable and
can be any of the four RXCK signals or four external
REFCK inputs (see Figure 14). The TXSYNC is
generated from the TXCK signal.
The RXCK pins are always defined as inputs and the
proper signal must be provided to each input.
4.3.1
The RXSYNC signal is used to align the incoming
DSTi data to retrieve all the T1 or E1 channels. The
RXSYNC pulse can be present for each PCM frame
(8Khz) or once per Superframe (every 12 or 24 PCM
frames). The period and position of the RXSYNC is
verified for each receive block independently. A status
bit (1 per link) in the RX Sync Status register is set if
the synchronization pulse occurs at an unexpected
time in the frame. The RX block will be re-aligned with
this new synchronization pulse.
4.3.2
The TXSYNC signal is used to align the outgoing
DSTo data to retrieve all the T1 or E1 channels.
When defined as input, the TXSYNC pulse can be
present for each PCM frame (8Khz) or once per
Superframe (every 12 or 24 PCM frames). The
bit 1
Clocking Options
Verification of the RXSYNC Period
Verification of the TXSYNC Period
problems
Bit Cell
bit 2
This may cause some inter-
when
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the
MT90220
is