MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 68

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

7.6
Tables 60 to 64 describe the External SRAM registers.
Address (Hex):
Synchronized access Set address before the transfer is initiated with the RX External SRAM Control
Reset Value (Hex):
Address (Hex):
Synchronized access Set address before the transfer is initiated with the RX External SRAM Control
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
7:0
7:0
4:3
2:0
7
6
5
External SRAM Register Description
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RX External SRAM Read/Write data register.
RX External SRAM Read/Write Address bit 7:0.
Write a 1 to reset the receiver. 0 means no action.
Write a 1 to reset the transmitter. 0 means no action.
Reserved, write 0 for normal operation.
Write 00 for normal system operation.
These 3 bits define the size of the external receive memory:
101: 2 banks of 512K x 8 bits
100: 1 bank of 512K x 8 bits
011: 2 banks of 128K x 8 bits
010: 1 bank of 128K x 8 bits
001: 2 banks of 32K x 8 bits
000: 1 bank of 32K x 8 bits
283
register
00
291
00
292
Defines the external SRAM configuration
08
register
Table 62 - RX External SRAM Read/Write Address 0
Table 61 - RX External SRAM Read/Write Data
Table 60 - SRAM Control Register
Description
Description
Description
MT90221
59