MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 22

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

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18-49
52-53
Byte
1-5
10
11
12
13
14
15
16
17
50
51
location is transmitted in all ICP cells, Stuff
Cells and Filler cells sent on all the links that
are part of the corresponding TX IMA group
Byte 7 - the TX Link ID register is used to set
the Link Logical ID and the cell type is
determined by the internal controller on a per
link basis
Byte 8 - the frame sequence number is
controlled by an internal counter
Byte 9 - the TX ICP Cell Offset register is used
to set the value. This value is inserted on a per
link basis
Byte 10 - the link Stuff indication is inserted
automatically and the advance indication option
is programmed by the TX IMA Control register
on a per link basis
Byte 11 - the SCCI is controlled by internal
circuitry. The SCCI is incremented by one for
each transfer of the TX ICP cell from the buffer
area to the TX Cell RAM.
Byte 13 - the value of M is programmed through
the TX Group Control Mode register
Byte 14 - the TX Group Control Mode register
is used to set the Transmit Timing Information
and define the reference link
Bytes 52 and 53 - the calculated CRC-10 Error
Control bits are inserted automatically
6
7
8
9
Group Status and Control
Link Status and Control
IMA Frame Sequence
Status Change Indic.
End-to-End Channel
Link Stuff Indication
CRC Error Control
ICP Cell Header
RX Test Pattern
TX Test Pattern
Cell ID, Link ID
ICP Cell Offset
Description
Test Control
OAM label
Sync. Info.
Unused
IMA ID
Content of Header is under S/W control. The HEC is calculated by H/W.
S/W control
The Link ID is programmed through other registers and inserted by H/W
Hardware Control
H/W Control. (Programmed by S/W through other registers)
H/W Control
H/W Control
S/W Control
S/W Control except for value of M
H/W Control (Programmed by S/W through other registers)
S/W Control
S/W Control
S/W Control
S/W Control
S/W Control
S/W Control
H/W Calculation
Table 2 - ICP Cell Description
Software controls all remaining bytes of the ICP
cells. It also maintains and updates all bytes that are
not directly controlled by the MT90221. A dedicated
address is reserved for each ICP cell byte for each of
the four IMA Groups. This permits direct access to
any of the bytes stored in each of the four ICP Cell
registers. Refer to Table 2, ICP Cell Description, for
details on the ICP cell byte contents.
To avoid updating or corruption problems, the
internal copy of the ICP Cell cannot be directly
accessed. ICP cells are prepared in a buffer area
(RAM inside the MT90221) and transfer commands
are issued to copy the content of the ICP cell into the
internal Cell RAM area and to start using this new
ICP cell. The MT90221 uses a flag (status bit) to
indicate that this transfer is underway. Changes
should not be made to the content of the ICP cell in
the buffer area until the transfer to the internal
memory is complete. The status bit is cleared during
the transfer and returns to ’1’ on completion of the
transfer. IMA Groups are controlled independently.
When access to the ICP cell of one group is
prohibited, the other ICP cell buffer areas can still be
updated. The TX ICP Cell Handler and TX ICP
Interrupt Enable registers are used to initiate a
transfer and enable an optional interrupt to indicate
when the process is complete.
Control Source
MT90221
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