SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 13

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
OVERALL DESCRIPTION
The SC28L202 is composed of several functional blocks. They are
listed in the approximate order of hierarchy as seen from the pins of
the device.
BRIEF DESCRIPTION OF FUNCTIONAL BLOCKS
Bus Interface
The Two basic modes of Bus Interface
The bus interface operates in “68K” or “x86” format as selected by
the I/M pin. The signals used by this section are the Address, Data
bus, Chip select, read/write, Data acknowledge and Interrupt
acknowledge and Interrupt request. Assertion of DACKN requires
two edges of the Sclk after the assertion of CEN. The default mode
is the x86 mode. Pin or register programming may change it to he
68K mode
Timing Circuits
Crystal Oscillator
The crystal oscillator is the main timing element for the 28L202. It is
nominally set at 14.7456 MHz. Operation with a crystal as a
frequency standard is specified from 7 MHz to 16.2 MHz The use of
an external clock allows all frequencies to 50 MHz. Clock prescalers
are provided to match various available system clocks to those
needed for baud rate generation.
Fixed Rate BRG
The BRG is the baud rate generator, is driven by the X1/Sclk input
through a programmable prescale divider. It generates all of the 27
“fixed” internal baud rates. This baud rate generator is designed to
generate the industry standard baud rates from a 14.7456 MHz
crystal or clock frequency. X1/Sclk frequencies different from
14.7456 MHz will cause the “fixed” baud rates to change by exactly
the ratio of 14.7456 to the different frequency.
Counter–Timer
The two counter–timers are programmable 16 bit “down” counters. It
provides miscellaneous baud rates, timing periods and acts as an
extra watchdog timer for the receivers. It has 8 programmable clock
sources derived from internal and external signals. It may also act
as a character counter for the receiver. Interrupts from the counter
timer are generated as it passes through zero.
Programmable BRG (PBRG)
This is another 16 bit programmable counter to generate only baud
rates or miscellaneous clock frequencies. Its output is available to
the receivers and transmitters and may be delivered to I/O ports. It
2000 Feb 10
Bus interface. 68K or x86 format
Timing Circuits
I/O Ports
UARTs
Transmitters and Receivers
FIFO Structures
Arbitrating Interrupt Structure
Character & Address Recognition
Flow Control
Test and Software compatibility with previous Philips (Signetics)
UARTs
Dual UART
NOTE: if an external clock is used X2 should not drive more
than 2 CMOS or 2 TTL equivalents.
7
has 8 programmable clock sources derived from internal and
external signals.
I/O ports
The SC28L202 is provided with 16 I/O ports. These ports are true
input and/or output structures and are equipped with a change of
state detector. The input circuit of these pins is always active. Under
program control the ports my display internal signals or static logic
levels. The functions represented by the I/O ports include hardware
flow control. Modem signals, signals for interrupt conditions or
various internal clocks and timing intervals. Noisy inputs to the I/O
ports are filtered (de–bounced) by a 38.4 KHz clock. Change of
state detectors are provided for each pin and are always available.
UARTs
The UARTs are fully independent, full duplex and provide all normal
asynchronous functions: 5 to 8 data bits, parity odd or even,
programmable stop bit length, false start bit detection. Also provided
are 256 byte FIFOs Xon/Xoff software flow. The BRG,
Counter–timer, or external clocks provide the baud rates. The
receivers and transmitters may operate in either the “1x” or “16x”
modes.
The control section recognizes two address schemes. One is the
subset of the other: a four (4) bit and an eight (7) bit address
spaces. The purpose of this is to provide a large degree of software
compatibility with previous Philips/Signetics UARTs.
Transmitters and Receivers
The transmitters and receivers are independent devices capable of
full duplex operation. Baud rates, interrupt and status conditions are
under separate control. Transmitters have automatic simplex
“turnaround”. Receivers have RTS and Xon/Xoff flow control and a
three character recognition system.
FIFO Structures
The FIFO structure is 256 bytes for each of the four FIFOs in the
DUART. They are organized as 11 bit words for the receiver and 8
bye words for the transmitter. The interrupt level may be set at any
value from 0 to 255. The interrupt level is independently set for each
FIFO.
FIFO interrupt and DMA fill/empty levels are controlled by the RxFIL
and TxFIL registers which may set any level of the from 0 to 255.
The signals associated with the FIFO fill levels are available to the
I/O pins (for interrupt or DMA) and to the arbitrating interrupt system
for “fine tuning” of the arbitration authority.
Intelligent Interrupt Arbitration
The interrupt system uses a highly programmable arbitrating
technique to establish when an interrupt should be presented to the
processor. The advantageous feature of this system is the
presentation of the context of the interrupt. It is presented in both a
current interrupt register and in the interrupt vector. The context of
the interrupt shows the interrupting channel, identifies which of the
18 possible sources in requesting interrupt service and in the case
of a receiver or transmitter gives the current fill level of the FIFO.
The content of the current interrupt register also drives the Global
Registers of the interrupt system. These registers are indirect
addresses (pointers) to the interrupt source requesting service.
Programming of Bid Control Registers allows the interrupt level of
any source to be varied at any time over a range of 256 levels.
Character and Address Recognition
The character recognition system is designed as a general–purpose
system. There is one for each UART. Each recognition block stores
Objective specification
SC28L202