SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 57

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
REGISTER MAPS
The registers of the SC28L202 are LOOSELY partitioned into two
groups: those used in controlling data channels and those used in
handling the actual data flow and status. Below is shown the general
configuration of all the register addressed. The ”Register Map
Summary” shows the configuration of the lower four bits of the
address that is the same for THE INDIVIDUAL UARTs. It also shows
the addresses for the several in the address space of UART A and
UART B that apply to the total chip configuration. The ”Register Map
Detail” shows the use of every address in the 8–bit address space.
2000 Feb 10
A(6:0)
000 0000 (0x00)
000 0001 (0x01)
000 0010 (0x02)
000 0011 (0x03)
000 0100 (0x04)
000 0101 (0x05)
000 0110 (0x06)
000 0111 (0x07)
000 1000 (0x08)
000 1001 (0x09)
000 1010 (0x0A)
000 1011 (0x0B)
000 1100 (0x0C)
000 1101 (0x0D)
000 1110 (0x0E)
000 1111 (0x0F)
001 0000 (0x10)
001 0001 (0x11)
001 0010 (0x12)
001 0011 (0x13)
001 0100 (0x14)
001 0101 (0x15)
001 0110 (0x16)
001 0111 (0x17)
001 1000 (0x18)
001 1001 (0x19)
001 1010 (0x1A)
001 1011 (0x1B)
001 1100 (0x1C)
001 1101 (0x1D)
001 1110 (0x1E)
001 1111 (0x1F)
Dual UART
READ
DEFAULT
Mode Register (MR0 A, MR1 A, MR2 A) DEFAULT
Status Register (SR A)
Receiver FIFO Register (RxFIFO A)
Mode Register (MR0 B, MR1 B, MR2 B) DEFAULT
Status Register (SR B)
Receiver FIFO Register (RxFIFO B)
EXTENSION
Receiver FIFO Fill Level (RxFL A)
Transmitter FIFO Empty level (TxEL A)
Receiver FIFO Fill Level (RxFL B)
Transmitter FIFO Empty level (TxEL B)
Input Port Change Register (IPCR) DEFAULT
Interrupt Status Register (ISR) DEFAULT
Counter Timer Value Register Upper (CTVU 0)
Counter Timer Value Register Lower (CTVL 0)
Interrupt Vector Register (IVR) GLOBAL
Input Port Register (IPR) I/O(6:0) A
Start Counter Command DEFAULT C/T 0
Stop Counter Command DEFAULT C/T 0
Enhanced Operation Status (EOS)
Input Port Change Register Upper (IPCRU A)
Input Port Change Register Lower (IPCRL A)
Input Port Register (IPR A)
Counter Timer Value Register Upper (CTVU 0)
Counter Timer Value Register Lower (CTVL 0)
Input Port Change Register Upper (IPCRU B)
Input Port Change Register Lower (IPCRL B)
Input Port Register (IPR B)
Counter Timer Value Register Upper (CTVU 1)
Counter Timer Value Register Lower (CTVL 1)
51
REGISTER MAP DETAIL (based on 28L92)
Register Map
NOTE: The register maps for channels A and B (UARTs A and B)
contain some control registers that configure the entire chip. These
are denoted by a ”” symbol
Addressing Scheme:
NOTE: Addresses 0x00 to 0x0F represent the “C92 Register” map
Default
A
WRITE
Mode Register (MR0 A, MR1 A, MR2 A) DEFAULT
Clock Select Register (CSR A) DEFAULT
Command Register (CR A) DEFAULT
Transmitter FIFO Register (TxFIFO A)
Mode Register (MR0 B, MR1 B, MR2 B) DEFAULT
Clock Select Register (CSR B) DEFAULT
Command Register (CR B) DEFAULT
Transmitter FIFO Register (TxFIFO B)
Command Register Extension (CRx A)
Command Register Extension (CRx B)
B
Interrupt Mask Register (IMR) DEFAULT
Interrupt Vector Register (IVR) GLOBAL
Output Port Configuration Register (OPCR)
Auxiliary Control Register (ACR) DEFAULT
Counter Timer Preset Register Upper (CTPU 0)
Counter Timer Preset Register Lower (CTPL 0)
Set Output Port Register (SOPR)
Reset Output Port Register (ROPR)
Set Output Port Register (SOPR A)
Reset Output Port Register (ROPR A)
I/O Port Configuration Register 0 (I/OPCR 0)
I/O Port Configuration Register 1 (I/OPCR 1)
Counter Timer Preset Register Upper (CTPU 0)
Counter Timer Preset Register Lower (CTPL 0)
Set Output Port Register (SOPR B)
Reset Output Port Register (ROPR B)
I/O Port Configuration Register 2 (I/OPCR 2)
I/O Port Configuration Register 3 (I/OPCR 3)
Counter Timer Preset Register Upper (CTPU 1)
Counter Timer Preset Register Lower (CTPL 1)
Extension
+8
+16
I/O(7:0)B
I/O(7:0)B
Objective specification
SC28L202
I/O(7:2)B