SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 30

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

1. Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
Philips Semiconductors
MR2 – Mode Register 2, A and B
MR2 can be accessed directly at 0x22 and 0x2A in the Extended section of the address map, or by means of the “MR Pointers” at the 0x00 and
0x08 address pointers used by legacy code.
The MR2 register provides basic channel setup control that may need more frequent updating.
NOTE:
MR2[7:6] – Mode Select
The DUART can operate in one of four modes: Normal, Automatic
Echo, Local Loop Back and Remote Loop Back
MR2[7:6] = b’00 Normal Mode
Normal and default mode The transmitter and receiver operating
independently.
MR2[7:6] = b’01 Automatic Echo
Places the channel in the automatic echo mode, which automatically
retransmits the received data. The following conditions are true
while in automatic echo mode:
MR2[7:6] = b’10 selects local loop back diagnostic mode. In this mode:
In this mode:
2000 Feb 10
MR2 [7:6] = b’11 Selects the Remote Loop back diagnostic mode.
MR2 A
MR2 B
Received data is re–clocked and re–transmitted on the TxD output.
The receiver clock is used for the transmitted data.
The receiver must be enabled, but the transmitter need not be
enabled.
The TxRDY and Tx Idle status bits are inactive.
The received parity is checked, but is not regenerated for
transmission, i.e., transmitted parity bit is as received.
Character framing is checked, but the stop bits are retransmitted
as received. Rx data is sent to RxFIFO
A received break is echoed as received until the next valid start bit
is detected.
CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
The transmitter output is internally connected to the receiver input.
The transmitter’s 1X clock is used for the receiver.
The TxD output is held high.
The RxD input is ignored.
The transmitter must be enabled, but the receiver need not be
enabled.
CPU to transmitter and receiver communications continue
normally.
Received data is re–clocked and re–transmitted on the TxD output.
The receiver 1X clock is used for the transmitted data.
Received data is not sent to the local CPU, and the error status
conditions are inactive.
The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received.
The receiver must be enabled, but the transmitter need not be
enabled.
Character framing is not checked, and the stop bits are
retransmitted as received.
Dual UART
Bit 7
CHANNEL MODE
00 = Normal
01 = Auto–Echo
10 = Local loop
11 = Remote loop
BIT 6
BIT 5
Tx CONTROLS
RTS
0 = No
1 = Yes
BIT 4
CTS
ENABLE Tx
0 = No
1 = Yes
24
BIT 3
STOP BIT LENGTH
NOTE: Add 0.5 to binary codes 0 – 7 for 5 bit character lengths.
0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875
2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
MR2[5] Transmitter Request to Send Control
This bit controls the deactivation of the RTSN output (I/O2) by the
transmitter. This output is manually asserted and negated by
appropriate commands issued via the command register. MR2 [5] = 1
negates (drives to logical 1) RTSN automatically one bit time after
the characters in the transmit shift register and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of
stop bits if the transmitter is not enabled). This feature can be used
to automatically terminate the transmission of a message as follows:
NOTE: when the transmitter controls the RTSN pin the meaning of
the pin is COMPLETELY changed. It has nothing to do with the
normal RTSN/CTSN “handshaking”. It is usually used to mean, “end
of message” and to “turn the line around” in simplex
communications. From a practical point of view the simultaneous
use of Tx control of RTSN and Rx control is mutually exclusive.
However if this is programmed the DUART performs as required.
MR2[4] – Clear to Send Control
The state of this bit determines if the CTSN input (I/O0) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the state of CTSN
each time it is ready to begin sending a character. If it is asserted
(low), the character is transmitted. If it is negated (high), the TxD
output remains in the marking state and the transmission is delayed
until CTSN goes low. Changes in CTSN, while a character is being
transmitted, do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 through 2 bits can be
programmed. In all cases, the receiver only checks for a mark
condition at the center of the first stop bit position (one bit time after
the last data bit, or after the parity bit if parity is enabled). If an
external 1X clock is used for the transmitter, MR2[1] = 0 selects one
stop bit and MR2[1] = 1 selects two stop bits to be transmitted.
A received break is echoed as received until the next valid start bit
is detected.
Program auto reset mode: MR2[5]= 1.
Enable transmitter.
Assert RTSN via command.
Send message.
Verify the next to last character of the message is being sent by
waiting until transmitter ready is asserted. Disable transmitter after
the last character is loaded into the TxFIFO.
The last character will be transmitted and RTSN will be reset one
bit time after the last stop bit.
BIT 2
BIT 1
BIT 0
Objective specification
SC28L202