SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 58

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
REGISTER MAP (BASED ON 28L92)
NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are
denoted by a ” ” symbol
2000 Feb 10
A(6:0)
010 0000 (0x20)
010 0001 (0x21)
010 0010 (0x22)
010 0011 (0x23)
010 0100 (0x24)
010 0101 (0x25)
010 0110 (0x26)
010 0111 (0x27)
010 1000 (0x28)
010 1001 (0x29)
010 1010 (0x2A)
010 1011 (0x2B)
010 1100 (0x2C)
010 1101 (0x2D)
010 1110 (0x2E)
010 1111 (0x2F)
011 0000 (0x30)
011 0001 (0x31)
011 0010 (0x32)
011 0011 (0x33)
011 0100 (0x34)
011 0101 (0x35)
011 0110 (0x36)
011 0111 (0x37)
011 1000 (0x38)
011 1001 (0x39)
011 1010 (0x3A)
011 1011 (0x3B)
011 1100 (0x3C)
011 1101 (0x3D)
011 1110 (0x3E)
011 1111 (0x3F)
Dual UART
READ
EXTENSION
Mode Register 0 (MR0 A) NEW ADDRESS
Mode Register 1 (MR1 A) NEW ADDRESS
Mode Register 2 (MR2 A) NEW ADDRESS
Mode Register 3 (MR3 A) NEW ADDRESS
Mode Register 0 (MR0 B) NEW ADDRESS
Mode Register 1 (MR1 B) NEW ADDRESS
Mode Register 2 (MR2 B) NEW ADDRESS
Mode Register 3 (MR3 B) NEW ADDRESS
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Receiver Clock Select Register (RxCSR B)
Transmitter Clock Select Register (TxCSR B)
Interrupt Status Register (ISR A)
Counter/Timer Clock Source (CTCS 0)
Programmable BRG Preset Lower (PBRGPL 0)
Programmable BRG Preset Upper (PBRGPU 0)
Counter/Timer Clock Source (CTCS 1)
Interrupt Status Register (ISR B)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Clock Source (PBRGCS)
Programmable BRG Preset Lower (PBRGPL 1)
Programmable BRG Preset Upper (PBRGPU 1)
Input Port Change Interrupt Enable (IPCE B)
52
WRITE
Mode Register 0 (MR0 A) NEW ADDRESS
Mode Register 1 (MR1 A) NEW ADDRESS
Mode Register 2 (MR2 A) NEW ADDRESS
Mode Register 3 (MR3 A) NEW ADDRESS
Mode Register 0 (MR0 B) NEW ADDRESS
Mode Register 1 (MR1 B) NEW ADDRESS
Mode Register 2 (MR2 B) NEW ADDRESS
Mode Register 3 (MR3 B) NEW ADDRESS
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Receiver Clock Select Register (RxCSR B)
Transmitter Clock Select Register (TxCSR B)
Counter/Timer Clock Source (CTCS 0)
Programmable BRG Preset Lower (PBRGPL 0)
Counter/Timer Clock Source (CTCS 1)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Preset Lower (PBRGPL 1)
Input Port Change Interrupt Enable (IPCE B)
Interrupt Mask Register (IMR A)
Programmable BRG Preset Upper (PBRGPU 0)
Interrupt Mask Register (IMR B)
Programmable BRG Clock Source (PBRGCS)
Programmable BRG Preset Upper (PBRGPU 1)
Objective specification
SC28L202