SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 36

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
ISR – Interrupt Status Register A and B
This register provides the status of all potential interrupt sources for
a UART channel. When generating an interrupt arbitration value, the
contents of this register are masked by the interrupt mask register
(IMR). If a bit in the ISR is a ’1’ and the corresponding bit in the IMR
is also a ‘1’; interrupt arbitration for this source will begin. If the
corresponding bit in the IMR is a zero, the state of the bit in the ISR
can have no affect on the IRQN output. Note that the IMR may or
may not mask the reading of the ISR as determined by GCCR[06].
If GCCR[0] is cleared, the reset and power on default, the ISR is
read without modification. If GCCR[0] is set, the read of the ISR
gives a value of the ISR ANDed with the IMR.
ISR[7] – Input Change of State.
This bit is set when a change of state occurs at the I/O1 or I/O0
input pins. It is reset when the CPU reads the Input Port Register,
IPR.
ISR[6] Fixed Watchdog Time–out.
This bit is set when the receiver’s watchdog timer has counted more
than 64 bit times since the last RxFIFO event. RxFIFO events are a
read of the RxFIFO or GRxFIFO, or the load of a received character
into the FIFO. The interrupt will be cleared automatically when the
RxFIFO or GRxFIFO is read. The receiver watch–dog timer is
included to allow detection of the very last characters of a received
message that may be waiting in the RxFIFO, but are too few in
number to successfully initiate an interrupt. Refer to the watchdog
timer description for details of how the interrupt system works after a
watchdog time–out.
ISR[5] – Address Recognition Status Change.
This bit is set when a change in receiver state has occurred due to
an Address character being received from an external source and
matches the reference address in ARCR. The bit and interrupt is
negated by a write to the CR with command x11011, Reset Address
Recognition Status.
ISR[4] – Xon/Xoff Status Change.
This bit is set when a Xon/Xoff character being received from an
external source. The bit is negated by a read of the channel
Xon/Xoff Interrupt Status Register, XISR.
ISR[3] – Counter Timer Status
The C/T has timed out or the count passed through 0. This bit is
cleared by issuing the “stop C/T ” command.
ISR[2] – Change in Channel Break Status.
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command via the CR.
2000 Feb 10
Dual UART
Bit 7
I/O Port
Change
of
state
Bit 6
Receiver
Watch–dog
Time–out
Bit 5
Address
recognition event
Bit 4
Xon/off
event
Bit 3
C/T
Ready
30
ISR[1] – RxINT. (Also Rx DMA hand shake at I/O pins)
The general function of this bit is to indicate that the RxFIFO has
data available and that it has entered the arbitration process. The
particular meaning of this bit is programmed by RxFIL register. If
programmed as receiver ready (MR2[3:2] = 00), it indicates that at
least one character has been received and is waiting in the RxFIFO
to be read by the host CPU. It is set when the character is
transferred from the receive shift register to the RxFIFO and reset
when the CPU reads the last character from the RxFIFO.
If RxFIL is programmed as FIFO full, ISR[1] is set when a character
is transferred from the receive holding register to the RxFIFO and
the transfer causes the RxFIFO to become full, i.e. all 256 FIFO
positions are occupied. It is reset whenever RxFIFO is not full. If
there is a character waiting in the receive shift register because the
FIFO is full, the bit is set again when the waiting character is
transferred into the FIFO.
The other two conditions of these bits, 3/4 and half full operate in a
similar manner. The ISR[1] bit is set when the RxFIFO fill level
meets or exceeds the value; it is reset when the fill level is less. See
the description of the MR2 register.
NOTE: This bit must be at a one (1) for the receiver to enter the
arbitration process. It is the fact that this bit is zero (0) when the
RxFIFO is empty that stops an empty FIFO from entering the
interrupt arbitration. Also note that the meaning if this bit is not quite
the same as the similar bit in the status register (SR).
ISR[0] – TxINT. (Also Tx DMA hand shake at I/O pins)
The general function of this bit is to indicate that the TxFIFO has an
at least one empty space for data. The particular meaning of the bit
is controlled by MR0 [5:4] indicates the TxFIFO may be loaded with
one or more characters. If MR0[5:4] = 00 (the default condition) this
bit will not set until the TxFIFO is empty – 256 bytes available. If the
fill level of the TxFIFO is below the trigger level programmed by the
TxINT field of the Mode Register 0, this bit will be set. A one in this
position indicates that at least one character can be sent to the
TxFIFO. It is turned off as the TxFIFO is filled above the level
programmed by MR0[5:4. This bit turns on as the FIFO empties.
(Note that the RxFIFO bit turns on as the FIFO fills.) This often a
point of confusion in programming interrupt functions for the receiver
and transmitter FIFOs.
NOTE: This bit must be at a one (1) for the transmitter to enter the
arbitration process. It is the fact that this bit is zero (0) when the
TxFIFO is full that stops a full TxFIFO from entering the interrupt
arbitration. Also note that the meaning if this bit is not quite the same
as the similar bit in the status register (SR).
Bit 2
Break
Change
Of
state
Bit 1
RxINT
Receiver entered the
arbitration process.
Bit 0
TxINT
Transmitter entered
the arbitration process.
Objective specification
SC28L202