SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 44

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
BCRx – Bidding Control Register – Xon/Xoff, A and B
This register provides the 8 MSBs of the Interrupt Arbitration number for a Xon/Xoff interrupt.
BCRA – Bidding Control Register – Address, A and B
This register provides the 8 MSBs of the Interrupt Arbitration number for an address recognition event interrupt.
BCR C/T – Bidding Control Register –C/T, 0 and 1
This register provides the 8 MSBs of the Interrupt Arbitration number for a counter/timer event interrupt.
BCRLBE – Bidding Control Register – Received Loop Back Error
This register provides the 8 MSBs of the Interrupt Arbitration number for the received loop back error interrupt.
Registers of the I/O ports
IPCRL – Input Port Change Register Lower Nibble, A and B (n = A for A, n = B for B)
This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each
pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b’0.
IPCRU – Input Port Change Register Upper Nibble, A and B (n = A for A, n = B for B)
This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each
pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b’0.
IPR – Input Port Register, A and B (n = A for A, n = B for B)
IPCE – Input Change Detect Enable, A and B (n = A for A, n = B for B)
IPCE[7:0] bits activate the input change of state detectors. If a pin is configured as an output, the change of state detectors, if enabled, continue
to be active and will show a change of state as the I/P port changes.
2000 Feb 10
Bit 7
change
0 = no change
1 = change
Bit 7
0 = no change
1 = change
Bits 7:0
Logical levels of I/O(7:0)n
Bit 7
0 = disable
1 = enable
I/O3 n
I/O7 n change
I/O7 n enable
Dual UART
Bits 7:0
MSBs of an Xon/Xoff interrupt bid
Bits 7:0
MSBs of an address recognition event interrupt bid
Bits 7:0
MSBs of a counter/timer event interrupt bid
Bits 7:0
MSBs of a received loop back error event interrupt bid
Bit 6
0 = disable
1 = enable
I/O6 n enable
Bit 6
change
0 = no change
1 = change
Bit 6
0 = no change
1 = change
I/O2 n
I/O6 n change
Bit 5
0 = disable
1 = enable
I/O5 n enable
Bit 7
change
0 = no change
1 = change
Bit 7
0 = no change
1 = change
I/O1 n
I/O5 n change
Bit 4
0 = disable
1 = enable
I/O4 n enable
Bit 6
change
0 = no change
1 = change
Bit 6
0 = no change
1 = change
I/O0 n
I/O4 n change
38
Bit 3
0 = disable
1 = enable
I/O3 n enable
Bit 3
I/O3 n state
Reads the actual logic level at the pin.
1 = high level; 0 = low level
Bit 3
I/O7 n state
Reads the actual logic level at the pin.
1 = high level; 0 = low level
Bit 2
0 = disable
1 = enable
I/O2 n enable
Bit 2
I/0n6 state
Bit 2
I/O2 n state
Bit 1
0 = disable
1 = enable
I/O1 n enable
Bit 1
I/O5 n state
Bit 1
I/O1 n state
Objective specification
SC28L202
Bit 0
0 = disable
1 = enable
I/O0 n enable
Bit 0
I/O4 n state
Bit 0
I/O0 n
state