SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 37

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
IMR – Interrupt Mask Register A and B
The programming of this register selects which bits in the ISR cause
an interrupt output. If a bit in the ISR is a ’1’ and the corresponding
bit in the IMR is a ’1’, the interrupt source is presented to the internal
interrupt arbitration circuits, eventually resulting in the IRQN output
being asserted (low). If the corresponding bit in the IMR is a zero,
the state of the bit in the ISR has no affect on the IRQN output.
IMR[7] COS enable
Allows a change of state in the inputs equipped with input change
detectors to cause an interrupt.
IMR[6] Fixed Watchdog Enable
Controls the generation of an interrupt watchdog timer event. If set,
a count of 64 idle bit times in the receiver will begin interrupt
arbitration.
IMR[5] Address recognition enable
Enables the generation of an interrupt in response to changes in the
Address Recognition circuitry of the Special Mode (multi–drop or
wake–up mode).
RxFIFO – Receiver FIFO, A and B
The FIFO for the receiver is 11 bits wide and 256 ”words” deep. The
status of each byte received is stored with that byte and is moved
along with the byte as the characters are read from the FIFO. The
upper three bits are presented in the STATUS register and they
change in the status register each time a data byte is read from the
FIFO. Therefor the status register should be read BEFORE the byte
is read from the RxFIFO if one wishes to ascertain the quality of the
byte
TxFIFO – Transmitter FIFO, A and B
The FIFO for the transmitter is 8 bits wide by 256 bytes deep. For character lengths less than 8 bits the upper bits will be ignored by the
transmitter state machine and thus are effectively discarded.
RxFIL – Receiver FIFO Interrupt Level, A and B
The position in the Rx FIFO that causes the receiver will enter the interrupt arbitration process. This register is used to offset the effect of the
arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also “equalize” interrupt latency and allow for larger
aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1.
RxFL – Receiver FIFO Fill Level Register
The number of bytes filled in the receiver FIFO
2000 Feb 10
Bits 7:0
8 data bits. MSBs set to 0 for 7, 6, 5 bit data
Bits 7:0
Any one of 256 FIFO fill positions
Bits 7:0
Channel byte count code ** (1) = implied ‘1’
00000001 = 1
00000010 = 2
to
11111111 = 255
**(1)00000000 = 256 if RxRDY status bit is set.
Dual UART
Bit 7
I/O Port Change of state
These bits are sent to the status register
Break
Received Status
Bit[10]
Bit[9]
Framing
Error Status
Bit 6
Rx Watch–dog
Time–out
Bit 5
Address
recognition event
Bit[8]
Parity
Error Status
31
IMR[4] Xon/Xoff Enable
Enables the generation of an interrupt in response to recognition of
an in–band flow control character.
IMR[3] Counter/Timer Enable
Enable the C/T interrupt when the C/T reaches 0 count.[2] Enables
the generation of an interrupt when a Break condition has been
detected by the channel receiver.
IMR[1] Receiver (Rx) Enable
Enables the generation of an interrupt when servicing for the
RxFIFO is desired.
IMR[0] Transmitter (Tx) Enable
Enables the generation of an interrupt when servicing for the
TxFIFO is desired.
The foregoing applies to the ”character error” mode of status
reporting. See MR1[5] and ”RxFIFO Status” descriptions for ”block
error” status reporting. Briefly, ”Block Error” gives the accumulated
error of all bytes received by the RxFIFO since the last “Reset Error”
command was issued. (CR = 0x04)
Bit 4
Xon/off
event
Bits [7:0]
This the data byte sent to the data bus or RxFIFO read
8 data bits
MSBs =0 for 7,6,5 bit data
Bit 3
C/T
Ready
Bit 2
Break Change
Of State
Bit 1
RxRDY
interrupt
Objective specification
SC28L202
Bit 0
TxRDY
interrupt