SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 35

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
SR – Channel Status Register A and B
SR[7] – Received Break
This bit indicates that an all zero character (including parity, if used)
of the programmed length has been received with a stop bit at a
logical zero. A single FIFO position is loaded with 0x00 when a
break is received; further entries to the FIFO are inhibited until the
RxD line returns to the marking state for at least one half bit time
(two successive edges of the internal or external 1x clock). When
this bit is set, the change in break bit in the ISR (ISR [2]) is set.
ISR[2] is also set when the end of the break condition, as defined
above, is detected. The break detect circuitry is capable of detecting
breaks that originate in the middle of a received character. However,
if a break begins in the middle of a character, it must last until the
end of the next character in order for it to be detected.
SR[6] – Framing Error (FE)
This bit indicates that a stop bit was not detected when an otherwise
non–zeros data character (including parity, if enabled) was received.
The stop bit check is made in the middle of the first stop bit position.
SR[5] – Parity Error (PE)
This bit is set when the ’with parity’ or ’force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In the special ’wake up mode’, the
parity error bit stores the received A/D bit.
SR[4] – Overrun Error (OE)
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of the
start bit of a new character when the RxFIFO is full and a character
is already in the receive shift register (257 valid characters in the
receiver) waiting for an empty FIFO position. When this occurs, the
character in the receive shift register (and its break detect, parity
error and framing error status, if any) is lost. This bit is cleared by a
reset error status command.
SR [3] – Transmitter Idle (Tx Idle)
This bit is set when the transmitter underruns, i.e., both the TxFIFO
and the transmit shift register are empty. It is set after transmission
2000 Feb 10
Dual UART
Bit 7
Received Break
0 = No
1 = Yes
Bit 6
Framing Error
0 = No
1 = Yes
Bit 5
Parity Error
0 = No
1 = Yes
Bit 4
Overrun Error
0 = No
1 = Yes
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of the last stop bit of a character, if no character is in the TxFIFO
awaiting transmission. It is negated when the TxFIFO is loaded by
the CPU, or when the transmitter is disabled or reset. This bit is
concerned with the transmitter transmitting data and it essentially
shows “ transmitter underrun”. If, while it is underrun it is
commanded to send an X on/Xoff character it will remain at the zero
state. If it is underrun and while sending an Xon/Xoff character the
TxFIFO is loaded then the bit will go low.
SR[2] – Transmitter Ready (TxRDY)
This bit, when set, indicates that the TxFIFO is ready to be loaded
with at least one more character. This bit is cleared when the
TxFIFO is full or is above its interrupt threshold level set in the MR
registers or TxFIFO interrupt Fill Level register (TxFIL). Characters
loaded in the TxFIFO while the transmitter is disabled will not be
transmitted.
SR[1] – RxFIFO Full (RxFULL)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all 256 RxFIFO positions are occupied. It is reset
when the CPU reads the RxFIFO and that read leaves one or more
empty byte position(s). If a character is waiting in the receive shift
register because the RxFIFO is full, RxFULL is not reset until the
second read of the RxFIFO since the waiting character is
immediately loaded to the RxFIFO.
SR[0] – Receiver Ready (RxRDY)
This bit indicates that a character has been received and is waiting
in the RxFIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the RxFIFO and reset
when the CPU reads the RxFIFO, and no more characters are in the
RxFIFO.
Bit 3
Tx Idle
0 = No
1 = Yes
Bit 2
TxRDY
0 = No
1 = Yes
Bit 1
RxFULL
0 = No
1 = Yes
Objective specification
SC28L202
Bit 0
RxRDY
0 = No
1 = Yes