SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 19

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
If the RxFIFO is full when a new character is received, the character
is held in the receiver shift register until a position is available in the
RxFIFO. At this time there are 257 valid characters in the RxFIFO. If
an additional character is received while this state exists, the
contents of the RxFIFO are not affected: the character previously in
the shift register is lost and the overrun error status bit, SR [4], will
be set upon receipt of the start bit of the new (overrunning)
character.
Wake Up Mode (Also the “9–bit”, “multi–drop”, “party; line” or
Special mode)
The SC28L202 provides four modes of this common asynchronous
”party line” protocol where the parity bit is used to indicate that a
byte is address data or information data. Three automatic modes
and the default Host operated mode are provided. The automatic
mode has several sub modes (see below). In the full automatic the
internal state machine devoted to this function will handle all
operations associated with address recognition, data handling,
receiver enables and disables. In both modes the meaning of the
parity bit is changed. It is often referred to as the A/D bit or the
address/data bit – sometimes the “9th” bit. It is used to indicate
whether the byte presently in the receiver shift register is an
”address” byte or a ”data” byte. A ”1” usually means address, a ”0”
data.
Its purpose is to allow several receivers connected to the same data
source to be individually addressed. Of course addressing could be
by group also. Normally the ”Master” would send an address byte to
all receivers ”listening”. The remote receiver will be “looking” at the
data stream for its address. Upon recognition of its address it will
enable itself to receive the following data stream. Upon receipt of an
address not its own it would then disable itself. As descried below
appropriate status bits are available to describe the operation.
Again, for this mode an “address byte” is a byte that has the bit in
the parity position set to logical 1.
The use of the multi–drop mode usually implies a “master and slave”
configuration of the several UART stations so programmed. The
software control should allow time for the slave stations to respond
to the receipt of an address bit. Often a reply from the addressed
station is expected to confirm the receipt of the address. Please see
control the automatic features of the address recognition in
MR0(1:0).
Enabling the Wake Up mode
(This mode is variously referred to as “9–bit” or “Multi–drop”.)
This mode is selected by programming bits MR1 [4:3] (the parity
bits) to ’11’. The wake up feature has four modes of operation: one
strictly under processor control and three automatic. These modes
are controlled by bits 6, 1, 0 in the MR3 register. Bit 6 controls the
loading of the address byte to the RxFIFO and MR0 [1:0] determines
the sub mode as shown in the following list.
MR3 [1:0] = 00 Normal Wake Up Mode (default) which is the same
as previous DUARTs and is therefore controlled by the processor.
The Host controls operation via interrupts it receives and commands
it writes to the DUART command registers (CR).
Normal Wake up (The default configuration)
The enabling of the wake–up mode executes a partial enabling of
the receiver state machine. Even though the receiver has been reset
the wake up mode will over ride the disable and reset condition.
In the default (mode “00” above and the least efficient) configuration
for this mode of operation, a ’master’ station transmits an address
character followed by data characters for the addressed ’slave’
station. The slave stations, whose receivers are normally disabled
2000 Feb 10
Dual UART
13
(not reset), examine the received data stream. Upon recognition of
its address bit (this is the parity bit redefined to indicate the
associated byte is an address bye – not the address itself)
interrupts the CPU (by setting RxRDY). The CPU (host) compares
the received address to its station address and enables the receiver
if it wishes to receive the subsequent data characters. Upon receipt
of another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit; the programmed
number of data bits, an address/data (A/D) bit and the programmed
number of stop bits. The CPU selects the polarity of the transmitted
A/D bit by programming bit MR1 [2]. MR1 [2] = 0 transmits a zero in
the A/D bit position which identifies the corresponding data bits as
data. MR1 [2] = 1 transmits a one in the A/D bit position which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bytes into the TxFIFO.
While in this mode, the receiver continuously looks at the received
data stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RxFIFO if the
received A/D bit is a one, but discards the received character if the
received A/D bit is a zero. If the receiver is enabled, all received
characters are transferred to the CPU via the RxFIFO. In either case
when the address character is recognized the data bits are loaded
into the data FIFO while the A/D bit is loaded into the status FIFO
position normally used for parity error (SR [5]). Framing error,
overrun error, and break detect operate normally whether or not the
receiver is enabled. When the automatic modes are in operation the
loading of the address character to the FIFO is controlled by the
MR0 (6) bit.
The several automatic controls. These modes are concerned with
the recognition of the address character itself
The enabling of the wake–up mode executes a partial enabling of
the receiver state machine. Even though the receiver has been reset
the wake up mode will over ride the disable and reset conditions.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled in the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re–enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
Receiver reset will discard the present shift register data, reset the
receiver ready bit (RxRDY), clear the status of the byte at the top of
MR3 [1:0] = 01 Auto wake. Enable receiver on address
recognition for this station. Upon recognition of its assigned
address the local receiver will be enabled by the character
recognition state machine and normal receiver communications
with the host will be established.
MR3 [1:0] = 10 Auto Doze. Disable receiver on address
recognition, not for this station. Upon recognition of an address
character that is not its own, in the Auto Doze mode, the receiver
will be disabled by the character recognition state machine and
the address just received either discarded or loaded to the
RxFIFO depending on the programming of MR0 [6].
MR3 [1:0] = 11 Auto wake and doze. Both modes described
above. The programming of MR3 [1:0] to 11 will enable both the
auto wake and auto doze features.
Objective specification
SC28L202