IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet

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... Description The IDT88K8483 is a 3-port SPI-4 Exchange device. The IDT SPI-4 Exchange devices build on IDT’s proven SPI-4 implementation and packet fragment processor (PFP) design. The IDT88K8483 suits appli- cations with slow backpressure response and other advanced networking applications when there is the need for duplicate ports to re- route data multiple times through the packet-exchange and temporary storage for complete in-flight packets ...

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... IDT IDT88K8483 Table Of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SPI-4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Insert and Extract paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Packet Fragment Processor (PFP QDR-II Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Embedded Processor Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Configuration Sequence ...

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... Figure 10. SPI-4 main to SPI-4 Tributary Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 11. PFP Loop Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 12. Microprocessor, Auxiliary and Internal Traffic Detector/Generator Data Path . . . . . . . 38 Figure 13. PFP Redirect Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 14. IDT88K8483 SPI-4 Connections Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 15. SPI-4 Ingress Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 16. SPI-4 Ingress State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 17. SPI-4 Egress State Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 18 ...

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... IDT IDT88K8483 Figure 54. JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 55. BR 672 FCBG Package Outline, RoHS compliant . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4 of 162 October 20, 2006 ...

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... IDT IDT88K8483 List of Tables Table 1. IDT88K8483 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 3. SPI-4 Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Table 4. Generic Interface - Control Field Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 5. Field Associated Non-Critical Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 6. Field Associated Critical Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 7. Non Field Associated Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 8. Time Base Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Table 9 ...

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... IDT IDT88K8483 Table 54. SPI-4 Ingress LP to LID Mapping Table (Block Base=0x0000, Register Offset=0x00-0xff .105 Table 55. SPI-4 Ingress Calendar 0 Table (Block Base=0x0100, Register Offset=0x00-0x3f/0x7f .105 Table 56. Ingress Calendar 1 Table (Block Base=0x0200, Register Offset=0x00-0x3f/0x7f .105 Table 57. SPI-4 Interface Enable Register (Block Base= 0x0300, Register Offset=0x00 .106 Table 58 ...

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... IDT IDT88K8483 Table 108. PFP Ingress Status Monitor Register - 3 (Block Base=0x1700/0x1F00, Register Offset=0x07 .126 Table 109. PFP Ingress Status Monitor Register - 4 (Block Base=0x1700/0x1F00, Register Offset=0x08 .126 Table 110. PFP Egress Status Monitor Register - 1 (Block Base=0x1700/0x1F00, Register Offset=0x09 .127 Table 111. PFP Egress Status Monitor Register - 2 (Block Base=0x1700/0x1F00, Register Offset=0x0A .127 Table 112 ...

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... IDT IDT88K8483 Table 162. Version Number Register (Block Base=0x8B00, Register Offset=0x30 .146 Table 163. Version Number Register (Block Base=0x8B00, Register Offset=0x32 .146 Table 164. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Table 165. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Table 166. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Table 167. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Table 168 ...

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... IDT IDT88K8483 Pin Assignment The following table shows the IDT88K8483 pins and their corresponding symbols. Function Pin ADR0 E1 ADR1 E2 ADR2 D2 ADR3 C4 ADR4 D3 ADR5 B4 BOND0 R6 BOND1 P6 CSB D5 DAT0 A5 DAT1 A4 DAT2 A3 DAT3 B3 DAT4 C3 DAT5 C2 DAT6 C1 DAT7 D1 DIV4 AB6 GPIO0 AE5 GPIO1 AD5 GPIO2 ...

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... QDR_D2 F23 QDR_D20 W26 QDR_D21 U25 QDR_D22 W25 QDR_D23 U24 QDR_D24 W24 QDR_D25 U23 QDR_D26 U22 QDR_D27 AC26 QDR_D28 AA26 QDR_D29 AC25 QDR_D3 H23 QDR_D30 Y25 QDR_D31 Y24 QDR_D32 AA23 QDR_D33 AA22 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... QDR_Q18 R26 QDR_Q19 T26 QDR_Q2 F22 QDR_Q20 V26 QDR_Q21 T25 QDR_Q22 V25 QDR_Q23 T24 QDR_Q24 V24 QDR_Q25 T23 QDR_Q26 T22 QDR_Q27 AB26 QDR_Q28 Y26 QDR_Q29 AB25 QDR_Q3 G23 QDR_Q30 AA25 QDR_Q31 AA24 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... SPI4A_ED[1]_N E17 SPI4A_ED[1]_P E16 SPI4A_ED[10]_N A19 SPI4A_ED[10_P A18 SPI4A_ED[11]_N E21 SPI4A_ED[11]_P E20 SPI4A_ED[12]_N D21 SPI4A_ED[12]_P D20 SPI4A_ED[13]_N D22 SPI4A_ED[13]_P E22 SPI4A_ED[14]_N C21 SPI4A_ED[14]_P C20 SPI4A_ED[15]_N B21 SPI4A_ED[15]_P B20 SPI4A_ED[2]_N D17 SPI4A_ED[2]_P D16 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... B18 SPI4A_EDCLK_N A21 SPI4A_EDCLK_P A20 SPI4A_ESCLK_N A7 SPI4A_ESCLK_P A6 SPI4A_ESCLK_T D6 SPI4A_ESTA[0]_N C7 SPI4A_ESTA[0]_P C6 SPI4A_ESTA[1]_N B7 SPI4A_ESTA[1]_P B6 SPI4A_ESTA_T0 E7 SPI4A_ESTA_T1 D7 SPI4A_ICTL_N E9 SPI4A_ICTL_P E8 SPI4A_ID[0]_N D9 SPI4A_ID[0]_P D8 SPI4A_ID[1]_N C9 SPI4A_ID[1]_P C8 SPI4A_ID[10]_N D13 SPI4A_ID[10]_P D12 SPI4A_ID[11]_N C13 SPI4A_ID[11]_P C12 SPI4A_ID[12]_N B13 SPI4A_ID[12]_P B12 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... SPI4A_ID[9]_P E12 SPI4A_IDCLK_N A15 SPI4A_IDCLK_P A14 SPI4A_ISCLK_N A23 SPI4A_ISCLK_P A22 SPI4A_ISCLK_T C24 SPI4A_ISTA[0]_N C23 SPI4A_ISTA[0]_P C22 SPI4A_ISTA[1]_N B23 SPI4A_ISTA[1]_P B22 SPI4A_ISTA_T0 D23 SPI4A_ISTA_T1 D24 SPI4A_LVDSSTA G21 SPI4A_RCLK E23 SPI4A_VREF B24 SPI4B_BIAS AF24 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... SPI4B_ED[3]_N AD17 SPI4B_ED[3]_P AD16 SPI4B_ED[4]_N AE17 SPI4B_ED[4]_P AE16 SPI4B_ED[5]_N AF17 SPI4B_ED[5]_P AF16 SPI4B_ED[6]_N AB19 SPI4B_ED[6]_P AB18 SPI4B_ED[7]_N AC19 SPI4B_ED[7]_P AC18 SPI4B_ED[8]_N AD19 SPI4B_ED[8]_P AD18 SPI4B_ED[9]_N AE19 SPI4B_ED[9]_P AE18 SPI4B_EDCLK_N AF21 SPI4B_EDCLK_P AF20 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... SPI4B_ID[13]_N AF13 SPI4B_ID[13]_P AF12 SPI4B_ID[14]_N AD15 SPI4B_ID[14]_P AD14 SPI4B_ID[15]_N AE15 SPI4B_ID[15]_P AE14 SPI4B_ID[2]_N AE9 SPI4B_ID[2]_P AE8 SPI4B_ID[3]_N AF9 SPI4B_ID[3]_P AF8 SPI4B_ID[4]_N AB11 SPI4B_ID[4]_P AB10 SPI4B_ID[5]_N AC11 SPI4B_ID[5]_P AC10 SPI4B_ID[6]_N AD11 SPI4B_ID[6]_P AD10 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... SPI4B_ISTA_T1 AC24 SPI4B_LVDSTA Y21 SPI4B_RCLK AB23 SPI4B_VREF AE24 SPI4M_BIAS AD1 SPI4M_CLK_SEL AE3 SPI4M_ECTL_N R4 SPI4M_ECTL_P P4 SPI4M_ED[0]_N R5 SPI4M_ED[0]_P P5 SPI4M_ED[1]_N U5 SPI4M_ED[1]_P T5 SPI4M_ED[10]_N W1 SPI4M_ED[10_P V1 SPI4M_ED[11]_N AA5 SPI4M_ED[11]_P Y5 SPI4M_ED[12]_N AA4 SPI4M_ED[12]_P Y4 SPI4M_ED[13]_N AB4 SPI4M_ED[13]_P AB5 SPI4M_ED[14]_N AA3 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... SPI4M_ED[3]_P T3 SPI4M_ED[4]_N U2 SPI4M_ED[4]_P T2 SPI4M_ED[5]_N U1 SPI4M_ED[5]_P T1 SPI4M_ED[6]_N W5 SPI4M_ED[6]_P V5 SPI4M_ED[7]_N W4 SPI4M_ED[7]_P V4 SPI4M_ED[8]_N W3 SPI4M_ED[8]_P V3 SPI4M_ED[9]_N W2 SPI4M_ED[9]_P V2 SPI4M_EDCLK_N AA1 SPI4M_EDCLK_P Y1 SPI4M_ESCLK_N G1 SPI4M_ESCLK_P F1 SPI4M_ESCLK_T F4 SPI4M_ESTA[0]_N G3 SPI4M_ESTA[0]_P F3 SPI4M_ESTA[1]_N G2 SPI4M_ESTA[1]_P F2 SPI4M_ESTA_T0 G5 SPI4M_ESTA_T1 G4 SPI4M_ICTL_N J5 SPI4M_ICTL_P H5 SPI4M_ID[0]_N J4 SPI4M_ID[0]_P H4 SPI4M_ID[1]_N J3 SPI4M_ID[1]_P H3 SPI4M_ID[10]_N N4 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... SPI4M_ID[3]_N J1 SPI4M_ID[3]_P H1 SPI4M_ID[4]_N L5 SPI4M_ID[4]_P K5 SPI4M_ID[5]_N L4 SPI4M_ID[5]_P K4 SPI4M_ID[6]_N L3 SPI4M_ID[6]_P K3 SPI4M_ID[7]_N L2 SPI4M_ID[7]_P K2 SPI4M_ID[8]_N L1 SPI4M_ID[8]_P K1 SPI4M_ID[9]_N N5 SPI4M_ID[9]_P M5 SPI4M_IDCLK_N R1 SPI4M_IDCLK_P P1 SPI4M_ISCLK_N AC1 SPI4M_ISCLK_P AB1 SPI4M_ISCLK_T AD3 SPI4M_ISTA[0]_N AC3 SPI4M_ISTA[0]_P AB3 SPI4M_ISTA[1]_N AC2 SPI4M_ISTA[1]_P AB2 SPI4M_ISTA_T0 AC4 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... G10 VDDA25 L8 VDDA25 L7 VDDA25 U8 VDDA25 U7 VDDA25 Y17 VDDA25 Y10 VDDC12 H17 VDDC12 H16 VDDC12 H15 VDDC12 H14 VDDC12 H13 VDDC12 H12 VDDC12 H11 VDDC12 H10 VDDC12 H9 VDDC12 H19 VDDC12 H18 VDDC12 J17 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... M10 VDDC12 M9 VDDC12 M19 VDDC12 M18 VDDC12 N10 VDDC12 N9 VDDC12 N19 VDDC12 N18 VDDC12 P10 VDDC12 P9 VDDC12 P19 VDDC12 P18 VDDC12 R10 VDDC12 R9 VDDC12 R19 VDDC12 R18 VDDC12 T10 VDDC12 T9 VDDC12 T19 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... W13 VDDC12 W12 VDDC12 W11 VDDC12 W10 VDDC12 W9 VDDC12 W19 VDDC12 W18 VDDH15 M26 VDDH15 AE26 VDDH15 B26 VDDH15 M20 VDDH15 N20 VDDH15 V20 VDDH15 W20 VDDH15 Y20 VDDH25 G19 VDDH25 Y19 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... VDDL25 AA8 VDDL25 AA18 VDDL25 F14 VDDL25 F9 VDDL25 F8 VDDL25 F18 VDDL25 G14 VDDL25 G9 VDDL25 G8 VDDL25 G18 VDDL25 H8 VDDL25 H7 VDDL25 P8 VDDL25 P7 VDDL25 V8 VDDL25 V7 VDDL25 W8 VDDL25 W7 VDDL25 Y14 VDDL25 Y9 VDDL25 Y8 VDDL25 Y18 VDDT33 A25 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... VSS K16 VSS K15 VSS K14 VSS K13 VSS K12 VSS K11 VSS K6 VSS L17 VSS L16 VSS L15 VSS L14 VSS L13 VSS L12 VSS L11 VSS L6 VSS M17 VSS M16 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... VSS T12 VSS T11 VSS T6 VSS U17 VSS U16 VSS U15 VSS U14 VSS U13 VSS U12 VSS U11 VSS U6 VSS V6 VSS W6 VSS Y7 VSS Y6 VSS M25 VSS AA16 VSS AA11 VSS F16 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... G15 VSS J8 VSS J7 VSS R8 VSS R7 VSS Y15 VSS AE1 VSS B1 VSS U21 VSS M13 VSS M12 VSS R12 VSS P12 VSS P14 VSS P15 VSS N13 VSS N15 VSS M15 VSS R14 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... IDT IDT88K8483 Function Pin VSS R15 VSS N14 VSS P13 VTT075 G20 VTT075 H20 VTT075 J20 VTT075 R20 VTT075 T20 VTT075 U20 A26 1 NP AF1 1 NP AF26 Table 1 IDT88K8483 Pinout (Part 162 October 20, 2006 ...

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... Pin Description Table The following table lists the functions of the pins provided on the IDT88K8483. Some of the functions listed are multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Analog signals ending with “P” are defined as being positive. Analog signals ending with “N” ...

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... IDT IDT88K8483 1 Symbol I/O Type SPI4A_ID[15:0]_P I LVDS SPI4B_ID[15:0]_P SPI4M_ID[15:0]_P SPI4A_ID[15:0]_N SPI4B_ID[15:0]_N SPI4M_ID[15:0]_N SPI4A_IDCLK_P I LVDS SPI4B_IDCLK_P SPI4M_IDCLK_P SPI4A_IDCLK_N SPI4B_IDCLK_N SPI4M_IDCLK_N SPI4A_ICTL_P I LVDS SPI4B_ICTL_P SPI4M_ICTL_P SPI4A_ICTL_N SPI4B_ICTL_N SPI4M_ICTL_N SPI4A_ISTA[1:0]_P O LVDS SPI4B_ISTA[1:0]_P SPI4M_ISTA[1:0]_P SPI4A_ISTA[1:0]_N SPI4B_ISTA[1:0]_N SPI4M_ISTA[1:0]_N SPI4A_ISCLK_P O LVDS SPI4B_ISCLK_P SPI4M_ISCLK_P SPI4A_ISCLK_N SPI4B_ISCLK_N SPI4M_ISCLK_N SPI4A_ISTA_T[1:0] O LVTTL ...

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... IDT IDT88K8483 1 Symbol I/O Type QDR_D[35:0]/ O HSTL G_ECTL[3:0], G_EDAT[31:0] QDR_Q[35:0]/ I HSTL G_ICTL[3:0], G_IDAT[31:0] QDR_RB O HSTL QDR_WB O HSTL QDR_K / G_ECLKP O HSTL QDR_KB / G_ECLKN O HSTL QDR_CQ / G_ICLKP I HSTL QDR_CQB / G_ICLKN I HSTL QDR_VREF / G_VREF I Analog Reference QDR_IMP / G_IMP I Reference Microprocessor Interface ADR[5:0] I CMOS DAT[7:0] / SDO ...

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... IDT IDT88K8483 1 Symbol I/O Type WRB/SDI I CMOS Pull-up Schmitt Trigger RDB / SCLK I CMOS Pull-up Schmitt Trigger CSB I CMOS Pull-up Schmitt Trigger INTB O CMOS Open Drain SPIEN I CMOS Pull-up MPM I CMOS Pull-up JTAG Interface TRSTB I CMOS Pull-up TCK I CMOS Pull-up Schmitt Trigger TMS ...

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... IDT IDT88K8483 1 Symbol I/O Type SPI4A_CLK_SEL I CMOS SPI4B_CLK_SEL Pull-up SPI4M_CLK_SEL Power Supply and Ground VDDC12 PWR VDDL12 PWR VDDH15 PWR VDDL25 PWR VDDH25 PWR VDDT33 PWR VDDA25 PWR VTT075 I/O VSS PWR BOND[1: table 2 Pin Description the external pins with multiple functions have both symbols in the Symbol column (column 1). In table1 IDT 88K8483 Pinout the external pins with multiple functions have only the first symbol in the Function column (column 1) ...

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... DATA PATH In normal operation, there are two paths through the IDT88K8483 device: the SPI-4A or SPI-4B ingress to SPI-4M egress path, and the SPI-4 M ingress to SPI-4A and SPI-4B egress path. SPI-4 burst sizes are separately configurable for each physical port. Data enter in bursts on a SPI-4 ingress interface and are sent to the SPI-4 ingress port buffers ...

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... IDT IDT88K8483 QDR-II External Memory Structure The device can be connected to 18M bits QDR-II (2M usable data bytes) SRAM which can store segments of 256 bytes as shown in Figure 5 QDR-II SRAM Structure Example LIDs, and allocate 128 segments (32Kbytes) to each LID as shown in PFP (508 segments, 127K bytes) Segment 507 ...

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... IDT IDT88K8483 SPI-4 Ingress Port Buffer Structure Each SPI-4 physical port in the ingress direction has 32 port buffers of 128 bytes as shown in Figure 7 SPI-4 Ingress Port Buffer Structure p.35. The buffers can be concatenated so that data flows from one FIFO into the next. Flow Control ...

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... IDT IDT88K8483 Data Path Detailed Description There are several data paths in the device as shown in the figures below. There are four PFPs in the device: PFP module A Tributary to Main (PFP-A-MT), PFP module A Main to Tributary (PFP-A-MT), PFP module B Trib- utary to Main (PFP-B-MT) and PFP module B Main to Tributary PFP-B-MT. ...

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... IDT IDT88K8483 SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4A Interface SPI-4 Egress SPI-4 Egress Port Buffers Tributary SPI-4s SPI-4 Egress SPI-4 Ingress SPI-4B Interface Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers PFP loop data path is sending data from PFP-A back to PFP-A or sending data from PFP-B back to PFP-B as shown in Data Path p ...

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... IDT IDT88K8483 SPI-4 Egress SPI-4 Ingress Port Buffer SPI-4A Interface SPI-4 Egress SPI-4 Egress Port Buffer Tributary SPI-4s SPI-4 Egress SPI-4 Ingress SPI-4B Interface Port Buffer SPI-4 Egress SPI-4 Egress Port Buffer Figure 12 Microprocessor, Auxiliary and Internal Traffic Detector/Generator Data Path ...

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... IDT IDT88K8483 External Interfaces The external interfaces provided on the IDT88K8483 device are three SPI-4 interfaces, SPI-4A, SPI-4B and SPI-4M, an interface to either a FPGA or a QDR-II bus, a pin-selectable serial or parallel microprocessor interface, a JTAG interface, and five general purpose input or output (GPIO) pins. The following information contains a set of the highlights of the features supported from the relevant standards, and a description of additional features implemented to enhance the usability of these interfaces for the system architect ...

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... IDT IDT88K8483 Serial microprocessor interface: – Compliance to Motorola Serial Peripheral Interface (SPI) specification – Byte access – Direct accessed space used for quick interrupt processing – Expanded indirect access space used for provisioning – Read operations to a reserved address or reserved bit fields return 0 – ...

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... The IDT88K8483 has three SPI-4 interfaces: one main SPI-4 interface (M) and two tributary SPI-4 interface (A and B). Each tributary SPI4 inter- face supports logical ports. The main SPI4 interface supports up to 128 logical ports. The logical port in-band address are from 0 to 255. ...

Page 42

... The status channel generates status frame, and controls the output skew per lane. SPI4A_ID[15:0]_P SPI4A_ID[15:0]_N SPI4A_IDCLK_P SPI4A_IDCLK_N SPI4A_ICTL_P SPI4A_ICTL_N SPI4A_ISTA[1:0]_P SPI4A_ISTA[1:0]_N SPI4A_ISCLK_P SPI4A_ISCLK_N SPI4A_ED[15:0]_P SPI4A_ED[15:0]_N SPI4A_EDCLK_P SPI4A_EDCLK_N SPI4A_ECTL_P SPI4A_ECTL_N SPI4A_ESTA[1:0]_P SPI4A_ESTA[1:0]_N SPI4A_ESCLK_P SPI4A_ESCLK_N V DDL25 V DDL12 3K 1% Network Processor Figure 14 IDT88K8483 SPI-4 Connections Example 42 of 162 October 20, 2006 ...

Page 43

... IDT IDT88K8483 Bit alignment Skew control Bit alignment The bit alignment block is responsible for data and clock alignment. The bit alignment allows the clock to be used for correct data sampling and eliminate bit errors by providing adequate set-up and hold time margins. ...

Page 44

... IDT IDT88K8483 OUT_OF_SYNCH IN_SYNCH The bus word may be payload data word, payload control word, idle control word or training word classified by the CTL input signal and the content of the control field. The DIP fields of the control word previous and subsequent payload data or training data are subjected to DIP checking. DIP checking is performed both in IN_SYNCH and OUT_OF_SYNCH state ...

Page 45

... IDT IDT88K8483 If the I_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after the last ‘11’ framing pattern. If I_CSW_EN is set to 1, and I_DIP_CSW is set to 1, then the DIP-2 is computed over calendar selection word and all preceding status indications after last ‘ ...

Page 46

... IDT IDT88K8483 Skew control Bit De-skew aligne Tx Machine Control words are inserted only between the transfers. Once a transfer has begun, the data words are sent uninterrupted until a whole transfer is complete. The interval between the end of a given transfer and the next payload control word consists of zero or more idle control words and training patterns ...

Page 47

... IDT IDT88K8483 Egress associated status channel Bit alignment The alignment selection is programed by AUTO_ALIGN flag in the The device is responsible for edge transition histogram for each lane. The data is sampled by 10-phased shifted clock during each clock cycle. Each consecutive pairs of sampled values are XORed and accumulated during a fixed observation window to generate transition edge histogram. ...

Page 48

... IDT IDT88K8483 If the E_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after last ‘11’ framing pattern. If E_CSW_EN field is set to 1, and E_DIP_CSW field is set to 1, then the DIP-2 is computed over calendar selection word and all preceding status indi- cations after last ‘ ...

Page 49

... IDT IDT88K8483 physical port SPI-4 logical port SPI-4 SPI 4 A SPI-4 SPI 4 B OBC insert extract The OBC insert and extract paths are provided on both directions of the packet fragment processor A. They are intended for low bandwidth communications channels like operation administration, maintenance functions etc. The OBC insert, inserts packets into the SPI4 stream via the OBC insert locker which is 256 bytes and packets from the SPI4 stream can be extracted via the OBC extract locker which is 256 bytes ...

Page 50

... IDT IDT88K8483 t+258 t+1 t OBC insert The first byte indicates the SOP or EOP and also whether the packet is error tagged or not by writing into the ED bit. The second byte is the lid information, which tells the OBC controller, which lid the packet goes to. The 3rd byte is the length of the packet in bytes. After this overhead is written, the packet is written into the OBC insert locker, not to exceed 256 bytes ...

Page 51

... IDT IDT88K8483 OBC extract The OBC extract process also works in the same way. The OBC extract FIFO can hold up to 256 bytes of data. The registers used in this process are PFP T-M extract control register (Register Offset=0x2) (p. 97) for the extract process is as follows ...

Page 52

... IDT IDT88K8483 Packet Fragment Processor (PFP) Overview SPI-4 SPI-4 Ingress Ingress Interface Port Buffer PFP The Packet Segment Pool (PFP internal block which is used for queuing and scheduling. There are four PFPs in the device - one for each SPI-4 tributary port and direction: PFP module A tributary to main (PFP-A-MT), PFP module A main to tributary (PFP-A-MT), PFP module B tributary to main (PFP-B-MT) and PFP module B main to tributary PFP-B-MT ...

Page 53

... IDT IDT88K8483 The egress also has the flexibility to be programmed for burst or non-burst mode and status or credit mode transfer control. When BURST_EN field in the PFP Flow Control Register (p. 125) the data buffer to the egress port buffer. If the burst mode is not enabled, then the LID can transfer only one segment of data at a time from the data buffer to the egress port buffer, and the PFP can schedule the next segment for the LID only after the current segment has been transmitted ...

Page 54

... IDT IDT88K8483 PFP Ingress Flow Control for over booking mode There are 4 main parameters for configuring the PFP ingress flow control for over booking mode: - Maximum number of segments per LID is configured in M field in the - Starving Free segments per LID is configured in THR_STARV field in the ...

Page 55

... The auxiliary interface has to be configured before the interface p.75. QDR_RB QDR_WR QDR_K QDR_KB QDR_CQ V /2 DDH15 100 OHM QDR_IMP Figure 23 IDT88K8483 and IDT7172604 QDR-II SRAM connections 129). The memory is managed based on memory segment size of 256byte 162 Auxiliary Interface Enable Register (p. SA[35:0] D[35:0] Q[35: ...

Page 56

... IDT IDT88K8483 QDR-II Flow Control The IDT88K8483 gets the QDR-II FIFO status information from the QDR-II interface, and the PFP LID status information from the PFP logic. The IDT88K8483 can be configured to one of two different flow control modes using the EBP_EN field in the (p ...

Page 57

... Channels Flow Control Mode 2 - Buffering In the buffering option the IDT88K8483 gets the data in interleaved mode or in packet mode and it sends the data in packet mode or in interleave mode. In this option, the EBC[2:0] field in the Figure 25 QDR-II FIFOs Allocation Example For Buffering Option In buffering option, the PFP and the QDR-II should be programed to packet mode by setting to 1 the PKT_MODE field in the Mode Control Registers (p ...

Page 58

... IDT IDT88K8483 An application example for flow control mode 2 is described in pressure. SPI-4 Ingress Ingress data Framer Interface status Interleaved Channels Impedance Matching Control The auxiliary interface egress side has impedance matching control. It has on chip test circuit that automatically adjusts the impedance of the auxil- iary interface egress data and control signals according to the 100 OHM pull down resistor that is connected to the QDR_IMP external signal ...

Page 59

... Ctrl[1] Ctrl[0] Ctrl[1] 129). The auxiliary interface has to be configured before the interface p.75. G_ICLKP V /2 DDH15 G_VREF 100 OHM G_IMP Figure 28 IDT88K8483 and FPGA connections DAT[31] CTL[ B3/Dummy B2/DM B6/DM B7/DM Figure 29 Generic Interface - Transfer Format for Normal Data 59 of 162 Auxiliary Interface Enable Register (p. ...

Page 60

... IDT IDT88K8483 The LID field in the Transfer Format for Normal Data includes the LID number (LID0,LID2,LID3,...). The control field is encoded to indicate the type of data word as described in Table 4. ctrl[1], ctrl[0] 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 ...

Page 61

... IDT IDT88K8483 Interface Operation The egress channel generates the transfer format and the local status information. The ingress channel detects the transfer format and status information from the adjacent device. Each word of the ingress interface is classified by decoding the control field. The reserved control field is ignored. The device extracts the LID from the first word of a transfer, and the following payload belongs to this LID ...

Page 62

... IDT IDT88K8483 Microprocessor Interface Overview The microprocessor interface can be in serial mode or in parallel mode. When the external signal SPIEN is cleared to 0, the interface is in parallel mode, and when SPIEN signal is set to 1, the interface is in serial mode. The parallel microprocessor interface can be connected directly to a suitable processor FPGA as shown in p ...

Page 63

... IDT IDT88K8483 Start ReadReg 0x16 ( EP_READY Result 1 1 ReadReg 0x14 ( IFIFO_STATUS Result 0 WriteReg 0x10 ( DATA Example for download sequence An example pseudo code of how the download sequence is implemented is shown below DOWNLOAD { Write RST=0x1 // RST field is in Global Software Reset Register (p. 90) Read EP_STATE ...

Page 64

... IDT IDT88K8483 } // End of Download Interrupt The device captures events in the Register (p. 98) are cleared by writing 1 to the appropriate field. The device has two interrupt levels: a primary level and a secondary level. The primary level status indicates the interrupt status of module A/B/ COMMON. The secondary level status indicates the interrupt status per module. ...

Page 65

... IDT IDT88K8483 PMON PMON Events There are few event types: Field associated non-critical event, Field associated critical event, Non field associated events. The events are described in the tables below. When a Field associated non-critical event is captured, the LID or LP (which is associated the event) is captured, and the table register records the latest captured LID or LP ...

Page 66

... IDT IDT88K8483 Event Name Tributary SPI4 ingress locker unavailable Main SPI4 ingress locker unavailable Tributary ingress data clock loss Tributary egress status clock loss Main ingress data clock loss Main egress status clock loss Tributary SPI4 DIP-2 Tributary SPI4 DIP-4 Tributary SPI4 bus error ...

Page 67

... IDT IDT88K8483 OBC Insert Loop Ingress 1 SPI4 A locker Ingress 2 SPI4 A locker Loop AUX insert OBC extract Loop 21 Egress SPI4 A locker 22 Egress SPI4 B locker Loop AUX extract Figure 33 PMON Measure Points 67 of 162 OBC ...

Page 68

... IDT IDT88K8483 Time base A single PMON time base is provided for the device. The time base can be generated internally or externally according to the INTERNAL field in PMON 1ms Timer Register (p. 145). The internal time base can be generated by a free running timer or OBC according to the TIMER field in the PMON 1ms Timer Register (p ...

Page 69

... TIM EBASE interrupt Clock IDT88K8483 has three programmable clock generators (main, tributary A and tributary B). One clock generator (main) is type M and two clock generators (tributary A and tributary B) are type T. There are three input clocks SPI4A_RCLK, SPI4B_RCLK and SPI4M_RCLK. Each one of the clock inputs is a clock source to one of the three internal clock generators ...

Page 70

... IDT IDT88K8483 Clock Generator Type M Clock generator type M generates the internal clock MCLK and the external SPI-4 main interface clocks (EDCLK, ISCLK, ISCLK_T) as shown in Figure 36 Clock Generator Type M generator source is the external signal SPI4M_RCLK. The MCLK frequency is selected by the N field in the The N field value can be modified at any time during normal operation ...

Page 71

... IDT IDT88K8483 Design Consideration System Reset There are two methods for resetting the IDT88K8483: hardware reset and software reset. During reset the output clocks are not toggled. Hardware Reset The RESETB input requires an active low pulse to reset the internal logic. Software Reset ...

Page 72

... IDT88K8483 JTAG Testing The IDT88K8483 supports board-level testing through the use of a JTAG test port. The test port comprises the following pins: JTDI (Test Data Input), TDO (Test Data Output), TMS (Test Mode Select), TCK (Test Clock), and TRSTB (Test Reset). The TCK clock frequency 10MHz. ...

Page 73

... Figure 40 TRSTB Signal During Power-On Reset VDD JTDO TDI TCK TCK TMS TMS TRSTB TRSTB IDT88K8483 - 1 Figure 39 JTAG Daisy Chain Figure 40 TRSTB Signal During Power-On Reset 73 of 162 p.73. Note that a falling TDI TDO TCK TCK TMS TMS TRSTB TRSTB IDT88K8483 - 2 October 20, 2006 ...

Page 74

... A bit can be enabled by the REFLECT_EN field in the the unused GPIO signals to an FPGA or microprocessor pins for debugging purpose. Power Supply The IDT88K8483 Power Supplies can be generated as shown in the design example in The IDT88K8483 system should have the following: tion Example p.75. 1. Connect the ...

Page 75

... VOUT GND TRIM 47uF RMT_ON_OFF V DDT33 470uF VIN VOUT GND TRIM 47uF RMT_ON_OFF DC-DC CONVERTOR Figure 41 IDT88K8483 Power Supply Generation Example Ferrite Bead 4.7uF V /V DDH25 DDL25 1uF Figure 42 IDT88K8483 VDDA25 Filter Circuit Ferrite Bead 4.7uF /V SPI4B_VRE SPI4C_VREF 1uF Figure 43 IDT88K8483 SPI4x_VREF Filter Circuit ...

Page 76

... IDT IDT88K8483 Configuration Sequence Before writing the configuration flow, design and determine the device configuration including: – Specific application – Data path – Mapping relation between link and logic port – Working mode of each link The device configuration flow is as follows: 1 ...

Page 77

... IDT IDT88K8483 Registers Register Organization: There are two types of register in the IDT88K8483: ◆ Direct Registers: Direct registers are used for high-priority registers such as interrupts and for access to the indirect registers. Direct registers can be accessed more quickly than indirect registers. All direct access registers are one byte wide. Direct registers used for accessing indirect registers are known as indirect access registers ...

Page 78

... IDT IDT88K8483 Direct Register Address (HEX) 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 The Indirect Register Accessing scheme: Address Name Segment Base 3 Module Base 2 Block Base 2 Register Offset 1 3 Byte Indirect register Address = 3 Byte Segment Base Address + Register Size (Bits) ...

Page 79

... IDT IDT88K8483 Indirect Read and Write Operation: ◆ Indirect Write Access Operation – The OBC reads the BUSY flag in the Microprocessor Indirect Access Control Register (p. 93). It proceeds only when the flag is cleared. – The indirect WRITE access operation is triggered by a write operation in the indirect access control register. This is achieved by setting field RWN the Microprocessor Indirect Access Control Register (p. 93). – ...

Page 80

... IDT IDT88K8483 Register Map Direct Registers Map Register Offset 0x1a ...

Page 81

... IDT IDT88K8483 Register Offset Indirect Registers Map ◆ Indirect Register Addressing = Segment Base Address + Module Base Address + Block Base Address + Register_Offset Segment Base Address There are five segments defined for indirect registers as shown in Table 16.. Only the USER_SEG is used by the users. ...

Page 82

... IDT IDT88K8483 Block Base Address and Register Offset There are block bases defined for module registers ( ) and for common ( ciated PMON, insert/extract Indirect Registers Map Module Block Base Base Name Address Address M:0x8000 CLK_GEN 0x0a00 M:0x8000 CLK_GEN 0x0a00 A:0x0000 LP2LID_MAP 0x0000 ...

Page 83

... IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 ...

Page 84

... IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG, 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 ...

Page 85

... IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A:0x0000 SPI_TIMING 0x0900 B:0x2000 M:0x8000 A:0x0000 SPI_TIMING 0x0900 B:0x2000 M:0x8000 A:0x0000 SPI_TIMING 0x0900 B:0x2000 M:0x8000 BUFFER_ TM - 0x1000 A (TM) ASSIGN B (TM 0x1800 A (MT) B (MT) PACKET_ TM - 0x1100 A (TM) LEN B (TM 0x1900 A (MT) ...

Page 86

... IDT IDT88K8483 Module Block Block Base Base Base Name Address Address PACKET_ TM - 0x1600 A (TM) MODE B (TM 0x1E00 A (MT) B (MT) PFP TM Control Register group - 0x1700 PFP MT Control Register group - 0x1F00 TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A (MT) B (MT) TM_PFP_REG TM - 0x1700 A (TM) B (TM) ...

Page 87

... IDT IDT88K8483 Module Block Block Base Base Base Name Address Address TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A (MT) B (MT) TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A (MT) B (MT) TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A (MT) B (MT) TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 ...

Page 88

... IDT IDT88K8483 Module Block Block Base Base Base Name Address Address TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A (MT) B (MT) B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 ...

Page 89

... IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT ...

Page 90

... A READ to unused/reserved bits returns 0 while a WRITE is ignored. Miscellaneous Registers Global Software Reset Register Read / Field Bits Write RST R/W 0:0 Note: Clocks generated by the IDT88K8483 are not affected by a software reset. Table 19 Microprocessor Registers Microprocessor Mailbox Input FIFO Data Register Read / Field Bits Write Data R/W ...

Page 91

... State 1 0 This field indicates whether the host CPU (WRITE side) or the IDT88K8483 (READ side) has control of the mailbox input IFIFO. 0:Host CPU (WRITE side) has control of IFIFO. Also indicates that the mailbox input FIFO is empty and data can be written to the FIFO by the host. ...

Page 92

... This flag indicates whether the chip is ready to download the firmware binary file from the host CPU. This flag is checked before the host CPU downloads to the IDT88K8483. This bit is cleared by reset and will go high after the chip is initialized. 0:Not ready for download. ...

Page 93

... IDT IDT88K8483 External Microprocessor Registers Microprocessor Indirect Access Control Register Read / Field Bits Write ERROR R 0:0 - 0:5 RWN R/W 0:6 BUSY R 0:7 Table 27 Microprocessor Indirect Access Control Register Error Code 0x3C 0x3D 0x3E 0x3F Microprocessor Indirect Access Data Register - 1 Read / Field ...

Page 94

... IDT IDT88K8483 Microprocessor Indirect Access Data Register - 2 Read / Field Bits Write DATA[8:15] R/W 0:0 - 0:7 Table 30 Microprocessor Indirect Access Data Register - 2 Microprocessor Indirect Access Data Register - 3 Read / Field Bits Write DATA[16:23] R/W 0:0 - 0:7 Table 31 Microprocessor Indirect Access Data Register - 3 Reset Length State 8 0 This register contains the second byte of the 4 byte data that written to or read from the indirect register ...

Page 95

... IDT IDT88K8483 Microprocessor Indirect Access Data Register - 4 Read / Field Bits Write DATA[24:31] R/W 0:0 - 0:7 Table 32 Microprocessor Indirect Access Data Register - 4 Microprocessor Indirect Access Address Register - 1 Read / Field Bits Write ADDRESS[0:7] R/W 0:0 - 0:7 Table 33 Microprocessor Indirect Access Address Register - 1 Microprocessor Indirect Access Address Register - 2 Read / Field ...

Page 96

... IDT IDT88K8483 PFP T-M insert control register for module A Read/ Field Bits Write DATA_AVAILABLE R/W 0:0 Note: The DATA_AVAILABLE flag will self clear if FIFO is emptied by PFP. This event will be forwarded to interrupt module. Reset Length State 1 0 This field indicates the availability of insert FIFO for T-M insertion. ...

Page 97

... IDT IDT88K8483 PFP T-M insert data register for module A Read/ Field Write DATA W PFP T-M extract control register for module A Read/ Field Write DATA_AVAILABLE R/W 0:0 Note: After data is extracted from the FIFO, a transfer extract event will be forwarded to the interrupt module. PFP T-M extract data register for module A ...

Page 98

... IDT IDT88K8483 PFP M-T extract control register for module A Read/ Field Write DATA_AVAILABLE R/W 0:0 Note: After data is extracted from the FIFO, a transfer extract event will be forwarded to the interrupt module. PFP M-T extract data register for module A Read/ Field Bits Write DATA R 0:0-0:7 Interrupt Registers Primary Interrupt Indication Register ...

Page 99

... IDT IDT88K8483 Primary Interrupt Enable Register Read / Field Bits Write MODULE_A_EN R/W 0:0 MODULE_B_EN R/W 0:1 COMMON_EN R/W 0:2 Table 45 Primary Interrupt Enable Register Note: Please refer to Interrupt Scheme (p. 64) Reset Length State 1 0 This field enables an interrupt to be generated if an event is captured in MODULE_A field in 0: Disable. ...

Page 100

... IDT IDT88K8483 Secondary Interrupt Module A Indication Register Read / Field Bits Write SPI-MT EXTRACT R/W 0:0 SPI-TM EXTRACT R/W 0:1 SPI-TM INSERT R/W 0:2 SPI-MTINSERT R/W 0:3 PMON R 0:4 Table 46 Secondary Module Indication Register Secondary Interrupt Module A Enable Register Read / Field Bits Write SPI- R/W 0:0 MTEXTRACT_EN SPI- R/W 0:1 TMEXTRACT_EN SPI-TMINSERT_EN R/W 0:2 SPI-MTINSERT_EN R/W 0:3 PMON_EN R/W 0:4 Note: Writing any field in this register, causes an interrupt to be generated based on the occurrence of that particular event indicated in the corresponding ...

Page 101

... IDT IDT88K8483 Secondary Interrupt Module B Indication Register Read / Field Write Reserved PMON R Table 48 Secondary interrupt module B Indication register(Register Offset=0xC) Secondary Interrupt Module B Enable Register Read / Field Bits Write Reserved 0:0 - 0:3 PMON_EN R 0:4 Table 49 Secondary Interrupt module B enable register (Register Offset=0xD) Reset Bits Length ...

Page 102

... IDT IDT88K8483 Secondary Interrupt COMMON Indication Register Read / Field Bits Write TIMEBASE R/W 0:0 INDIRECT_ACC R/W 0:1 I_FIFO_READY R/W 0:2 I_FIFO_OFLOW R/W 0:3 O_FIFO_MSG R/W 0:4 SOC R/W 0:5 10ms R/W 0:6 Table 50 Interrupt secondary COMMON indication register (Register Offset=0xe) Reset Length State 1 0 This field indicates an event captured in the timebase. Read 0: No event is generated. ...

Page 103

... IDT IDT88K8483 Secondary Interrupt COMMON Enable Register Read / Field Bits Write TIMEBASE_EN R/W 0:0 INDIRECT_ACC_EN R/W 0:1 I_FIFO_READY_EN R/W 0:2 I_FIFO_OFLOW_EN R/W 0:3 O_FIFO_MSG_EN R/W 0:4 SOC_EN R/W 0:5 10ms_EN R/W 0:6 Note: Writing any field in this register, causes an interrupt to be generated based on the occurrence of that particular event indicated in the corresponding field in Table 50. The interrupt appears as an active low on the INTB pin in the microprocessor interface. ...

Page 104

... IDT IDT88K8483 Indirect Registers Description Note: (1) All indirect registers are 32 bits wide. (2) Treat unused bits as reserved bits. (3) A READ to unused/reserved bits returns 0 while a WRITE is ignored. Clock Registers MCLK Divider Sticky Register Read / Field Bits Write N R/W 0:0-0:1 Note: (1) “Sticky” means that the register value does not change during software reset. ...

Page 105

... Note: (1)There are 128 table entries for SPI-4 main interface and 64 table entries for SPI-4 tributary interface. (2)The IDT88K8483 and the attached device must have identical calendars for ingress and the attached egress device. Table 56 Ingress Calendar 1 Table (Block Base=0x0200, Register Offset=0x00-0x3f/0x7f) ...

Page 106

... IDT IDT88K8483 SPI-4 Interface Enable Register Read / Field Bits Write SPI4_EN R/W 0:0 SPI4_PDN R/W 0:1 Note: (1) The SPI4 interface has to be configured before enabling the interface SPI-4 Interface Enable Register (Block Base= 0x0300, Register Offset=0x00) Table 57 SPI-4 Ingress Configuration Register Read / Field Bits Write ...

Page 107

... IDT IDT88K8483 SPI-4 Ingress Training Parameter Register Read / Field Bits Write FIFO_MAX_T R/W 0:0-2:7 ALPHA_FIFO R/W 3:0-3:7 Note: The purpose of the FIFO status path training sequence is for the deskew of bit arrival times on the FIFO status and control lines. SPI-4 Ingress Training Parameter Register (Block base=0x0300, Register Offset=0x02) Table 59 SPI-4 Ingress Calendar 0 Configuration Register ...

Page 108

... IDT IDT88K8483 SPI-4 Ingress Calendar 1 Configuration Register Read / Field Bits Write I_CAL_M R/W 0:0-0:7 I_CAL_LEN R/W 1:0-1:6 Note the I_CSW_EN bit in SPI4 Ingress Calendar Switch Control Register (p. 109) calendar sequence is repeated before a DIP2 parity,’1 1’ framing word and calendar selection word are inserted. ...

Page 109

... IDT IDT88K8483 SPI-4 Ingress Diagnostics Register Read / Field Bits Write I_FORCE_TRAIN R/W 0:0 I_ERR_INS R/W 0:1 I_DIP_NUM R/W 0:2-0:5 Note: The purpose of the status channel training sequence is for the deskew of status and clock signals and for the alignment between the 2 status signals. SPI-4 Ingress Diagnostics Register (Block base=0x0300, Register Offset=0x06) ...

Page 110

... IDT IDT88K8483 CAL_SEL I_CSW_EN I_DIP_CSW I_CSW_EN SPI-4 Ingress Fill Level Register Read / Field Bits Write FILL_CUR R 0:0-0:5 SPI-4 Ingress Fill Level Register (Block base=0x0300, Register offset=0x0B-0x0C) Table 68 There are 2 registers for SPI-4 main interface. SPI-4 Ingress Max Fill Level Register ...

Page 111

... IDT IDT88K8483 SPI-4 Ingress WATERMARK Register Read / Field Bits Write WATERMARK R/W 0:0-0:4 Note:(1) 0x1F is the highest watermark that can be set, meaning that the ingress buffer will be full before backpressure will be initiated on a SPI-4 ingress inter face PFP. A WATERMARK field value of 0x0F is used to set a watermark for a half-full ingress buffer before tripping backpressure. ...

Page 112

... IDT IDT88K8483 SPI-4 Egress Calendar 1 Table. Read / Field Bits Write LP R/W 0:0-0:7 SPI-4 Egress Calendar 1 Table (Block Base=0x0600, Register Offset=0x00-0x3F/0x7F) Table 74 There are 128 table entries for SPI-4 main egress and 64 table entries for SPI-4 tributary egress calendar_1 to schedule the updating of the status ...

Page 113

... IDT IDT88K8483 SPI-4 Egress Configuration Register Read / Field Bits Write E_INSYNC_THR R/W 0:0-0:4 E_CLK_EDGE R/W 0:5 E_LOW R/W 0:6 NOSTAT R/W 0:7 E_OUTSYNC_THR R/W 1:0-1:3 Note: Please refer to SPI-4 Ingress State Machine (p. 44) for an illustration of out of sync and in sync state. SPI-4 Egress Configuration Register (Block Base=0x0800, Register Offset=0x01) Table 75 SPI-4 Egress Training Parameter Register ...

Page 114

... IDT IDT88K8483 SPI-4 Egress Calendar 0 Configuration Register Read / Field Bits Write E_CAL_M R/W 0:0-0:7 E_CAL_LEN R/W 1:0-1:6 Note the E_CSW_EN bit in SPI-4 Egress Calendar Switch Control Register (p. 116) calendar sequence is repeated before a DIP2 parity,’1 1’ framing word and calendar selection word are inserted. ...

Page 115

... IDT IDT88K8483 SPI-4 Egress Status Register Read / Field Bits Write E_SYNCV R 0:0 E_DSK_OOR R 0:1 SCLK_AV R 0:2 SPI-4 Egress Status Register (Block Base=0x0800, Register Offset=0x05) Table 79 SPI-4 Egress Diagnostics Register Read / Field Bits Write E_FORCE_TRAIN R/W 0:0 E_ERR_INS R/W 0:1 E_DIP_NUM R/W 0:2-0:5 BIT_DELAY R/W 0:6-0:7 Note: The purpose of the data path training sequence is for the deskew of data and clock signals and for the alignment between the 16 data signals. ...

Page 116

... IDT IDT88K8483 SPI-4 Egress Calendar Switch Control Register Read / Field Bits Write E_CSW_EN R/W 0:0 CAL_ID R 0:1 E_DIP_CSW R/W 0:2 Note: Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) for more details about calendar implementation. SPI-4 Egress Calendar Switch Control Register (Block Base = 0x0800, Register Offset=0x08) Table 82 ...

Page 117

... IDT IDT88K8483 SPI-4 Histogram Measure Launch Register Read / Field Bits Write LANE R/W 0:0-0:4 Note: The manual bit alignment is a edge transition histogram measure process. Please refer to Figure 15(Ingress block diagram) and subsequent description for histogram overview. In normal operation bit alignment is automatic and these registers are not used. ...

Page 118

... IDT IDT88K8483 SPI-4 Bit Alignment Result Register Read / Field Bits Write TAP[7:0] R/W 0:0-0:7 Note: Please refer to SPI-4 Ingress Block Diagram (p. 43) and SPI-4 Egress State Block Diagram (p. 46) for bit alignment overview. Table 88 SPI-4 Bit Alignment Result Register (Block Base=0x0900 Register Offset=0x0C-0x1E) ...

Page 119

... IDT IDT88K8483 SPI-4 Egress Data Clock Timing Register Read / Field Bits Write DCTC[0:3] R/W 0:0-0:3 Table 91 SPI-4 Egress Data Clock Timing Control (BlockBase=0x0900, Register Offset=0x2C) SPI-4 Egress Status Timing Register Read / Field Bits Write STC0[0:1] R/W 0:0-0:1 STC1[0:1] R/W 0:2-0:3 Table 92 SPI-4 Egress Status Timing Control (Block Base=0x0900, Register Offset=0x2D) ...

Page 120

... IDT IDT88K8483 SPI-4 Egress Status Clock Timing Register Read / Field Bits Write SCTC[0:3] R/W 0:0-0:3 SPI-4 Egress Status Clock Timing Control (Block Base=0x0900, Register Offset=0x2E) Table 93 Packet Fragment Processor (PFP) Registers PFP Buffer Segment Assign Table Read / Field Bits Write M R/W 0:0-1:0 Reserved R 1:1-1:7 THR_STARV R/W 2:0-2:7 THR_HUNG ...

Page 121

... IDT IDT88K8483 PFP Packet Length Thresholds Read / Field Bits Write LEN_MIN R/W 0:0-0:7 Reserved R/W 1:0-1:7 LEN_MAX R/W 2:0-3:5 Table 95 PFP Packet Length Thresholds There are 64 registers in this table, one for each LID. PFP Queue Diagnose Table Read / Field Bits Write UNIT R/W 0:0-1:1 Reserved R 1:2-2:3 READ_POINTER R/W 2:4-3:7 Table 96 PFP Queue Diagnose Table (Block Base=0x1200/0x1A00, Register Offset=0x00-0x3F) There are 64 registers in this table, one for each LP ...

Page 122

... IDT IDT88K8483 PFP Egress Burst Size Table Read / Field Bits Write MAX_BURST_S R/W 0:0-0:3 MAX_BURST_H R/W 0:4-0:7 Note: The MAX_BURST_H and MAX_BURST_S values relate to MaxBurst2 and MaxBurst1 parameters in the OIF SPI-4 implementation agreement (OIF-SPI-4- 02.1). Table 98 PFP Egress Burst Size Table (Block Base=0x1400/0x1C00, Register Offset=0x00-0x3F) There are 64 registers in this table, one for each LID. ...

Page 123

... Length State 3 0 Link Identifier (LID) number configuration. Configures the maximum number of LIDs that the application will use for this PFP data buffer. Once configured this value should not be changed without resetting the IDT88K8483. NR_LID Maximum number of LIDs 000 1 001 4 010 ...

Page 124

... IDT IDT88K8483 PFP Queue Weighting Enable Register Read / Field Bits Write WEIGHT_EN R/W 0:0 Note: Please refer to page 52 for a detailed explanation of PFP priority and scheduling. Table 103 PFP Queue Weighting Enable Register Reset Length State 1 0 This field selects which LID data needs to be transmitted first according to its priority set in the field WEIGHT in when non-satisfied status information is received in the FIFO status channel ...

Page 125

... IDT IDT88K8483 PFP Flow Control Register Read / Field Bits Write CREDIT_EN R/W 0:0 BURST_EN R/W 0:1 Table 104 PFP Flow Control Register (Block Base=0x1700/0x1F00, Register Offset=0x03) PFP Test Register Read / Field Bits Write REPEAT R/W 0:0 SINGLE_REP R/W 0:1 LID_REPEAT R/W 0:2-0:7 STOP R/W 1:0 SINGLE _STOP R/W 1:1 LID_STOP R/W 1:2-1:7 Table 105 PFP Test Register ...

Page 126

... IDT IDT88K8483 PFP Ingress Status Monitor Register - 1 Read / Field Bits Write STATUS[0] R 0:0-0:1 STATUS[1:15] R 0:2-3:7 Note: (1) The status has the same definition as described in the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) [MSB, LSB] Status 10 Satisfied 01 Hungry 00 Starving 11 Reserved (2) The ingress status reflects the status based on the data buffer fill level. ...

Page 127

... IDT IDT88K8483 PFP Egress Status Monitor Register - 1 Read / Field Bits Write STATUS[0:15] R 0:0-3:7 Note: (1) The egress status has the same definition as described in the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) and is shown in tus Monitor Register - 1 (p. 126) (2) The egress status reflects the status received from the status channel. ...

Page 128

... IDT IDT88K8483 PFP Maximum Packet Length Register Read / Field Bits Write MAX_LEN R/W 0:0-0:5 Table 115 PFP Maximum Packet Length Register (Block Base=0x1700/0x1F00, Register Offset=0x0E) Reset Length State 6 6 This indicates the maximum packet length of the PFP. If maximum packet length is greater than or equal to MAX_LEN*256 bytes, the ingress server will truncate the packet, add SOP/EOP, add error tag accordingly and send cut-down event to PMON ...

Page 129

... IDT IDT88K8483 Auxiliary Registers Auxiliary Interface Enable Register Read / Field Bits Write AUX_EN R/W 0:0 AUX_PDN R/W 0:1 1 Note: The interface has to be configured before enabling it.This is done in Auxiliary Interface Configuration Register (p. 129) 2 The interface has to be powered down before configuring it to the QDR-II interface mode or the generic interface mode ...

Page 130

... IDT IDT88K8483 Auxiliary Clock Monitor Status Register) Read / Field Bits Write NCLKAV R 0:0 PCLKAV R 0:1 Note: Refer to Table 2 “Pin Description” on page 28 for a brief description of the QDR-II clocks. Table 120 Auxiliary Clock Monitor Status Register External Memory Test Control Register Read / Field Bits ...

Page 131

... IDT IDT88K8483 External Memory Test Results Register Read / Field Bits Write TEST_DONE R 0:0 ERROR R 0:1 Table 122 External Memory Test Results Register Auxiliary Early Backpressure Threshold Register Read / Field Bits Write EBP_THR R/W 0:0-1:5 Table 123 Auxiliary Early Backpressure Threshold Register Auxiliary Packet Mode Configuration Register ...

Page 132

... IDT IDT88K8483 Auxiliary Automatic Impedance Matching Control Register Read / Field Bits Write AUTO_MEASURE R/W 0:0 Note: This register is used for diagnostic purpose only. Table 126 Auxiliary Automatic Impedance Matching Control Register (Block Base=0x0A00, Register Offset=0x0F) Auxiliary Synchronization Status Register Read / Field Bits Write ...

Page 133

... IDT IDT88K8483 Auxiliary Initialization Control Register Read / Field Bits Write INIT_TRIG R/W 0:0 AUTO_SYNCH R/W 0:1 Table 128 Auxiliary Initialization Control Register PRGD Registers Enable Control Register Read/ Field Bits Write GEN R/W 0:0 DEN R/W 0:1 Table 129 Enable Control Register Feedback Configuration Register Read/ Field Bits Write ...

Page 134

... IDT IDT88K8483 Packet Length Register Read/ Field Write P_LEN R/W 0:0 - 1:5 Table 133 Packet Length Register (Block Base=0x0B00, Register Offset=0x03) Burst Size Register Field Read/Write BURST_S R/W Table 134 Burst Size Register (Block Base=0x0B00, Register Offset=0x04) Random Control Register Field Read/Write PLEN_RAND R/W BURST_RAND R/W Table 135 Random Control Register (Block Base=0x0B00, Register Offset=0x05) ...

Page 135

... IDT IDT88K8483 LID Register Read/ Field Write LID R/W Synchronization Register Read/ Field Write SYNCV R/W 0:0 SYNCI R/W 0:1 Note: (1)The out of sync status can be due to any one of 3 reasons. a) Resetting the device field “DEN” in Enable Control Register (p. 133 excessive errors between regenerated sequence from the received data and received sequence. ...

Page 136

... IDT IDT88K8483 PMON Event Interrupt Indication Register Read / Field Bits Write T_INACT_I R/W 0:0 M_INACT_I R/W 0:1 TM_ISOP_I R/W 0:2 TM_IEOP_I R/W 0:3 MT_ISOP_I R/W 0:4 MT_IEOP_I R/W 0:5 TM_PKTCD_I R/W 0:6 MT_PKTCD_I R/W 0:7 T_LOCKUN_I R/W 1:0 M_LOCKUN_I R/W 1:1 T_DCLKLOS_I R/W 1:2 Table 139 PMON Event Interrupt Indication Register (Block Base=0x0F00, Register Offset=0x00) Reset Length State 1 0 Tributary ingress inactive LP event. ...

Page 137

... IDT IDT88K8483 Read / Field Bits Write T_SCLKLOS_I R/W 1:3 M_DCLKLOS_I R/W 1:4 M_SCLKLOS_I R/W 1:5 T_DIP2_I R/W 1:6 T_DIP4_I R/W 1:7 T_BUSERR_I R/W 2:0 T_ISYNC_I R/W 2:1 T_ESYNC_I R/W 2:2 M_DIP2_I R/W 2:3 M_DIP4_I R/W 2:4 Table 139 PMON Event Interrupt Indication Register (Block Base=0x0F00, Register Offset=0x00) Reset Length State 1 1 Tributary egress status clock loss event. Read 1: Indicates that the event has not occurred. ...

Page 138

... IDT IDT88K8483 Read / Field Bits Write M_BUSERR_I R/W 2:5 M_ISYNC_I R/W 2:6 M_ESYNC_I R/W 2:7 Table 139 PMON Event Interrupt Indication Register (Block Base=0x0F00, Register Offset=0x00) Reset Length State 1 0 Main SPI4 bus error event. Read 1: Indicates occurrence of the event. Read 0: Indicates that the event has not occurred. ...

Page 139

... IDT IDT88K8483 PMON Event Interrupt Enable Register Read / Field Bits Write T_INACT_EN R/W 0:0 M_INACT_EN R/W 0:1 TM_ISOP_EN R/W 0:2 TM_IEOP_EN R/W 0:3 MT_ISOP_EN R/W 0:4 MT_IEOP_EN R/W 0:5 TM_PKTCD_EN R/W 0:6 MT_PKTCD_EN R/W 0:7 T_LOCKUN_EN R/W 1:0 M_LOCKUN_EN R/W 1:1 T_DCLKLOS_EN R/W 1:2 T_SCLKLOS_EN R/W 1:3 M_DCLKLOS_EN R/W 1:4 M_SCLKLOS_EN R/W 1:5 T_DIP2_EN R/W 1:6 Table 140 PMON Event Interrupt Enable Register (Block Base=0x0F00, Register Offset=0x01) Reset Length State 1 0 Tributary ingress inactive LP. ...

Page 140

... IDT IDT88K8483 Read / Field Bits Write T_DIP4_EN R/W 1:7 T_BUSERR_EN R/W 2:0 T_ISYNC_EN R/W 2:1 T_ESYNC_EN R/W 2:2 M_DIP2_EN R/W 2:3 M_DIP4_EN R/W 2:4 M_BUSERR_EN R/W 2:5 M_ISYNC_EN R/W 2:6 M_ESYNC_EN R/W 2:7 Note: Writing any field in this register, causes an interrupt to be generated based on the occurrence of that particular event indicated in the corresponding field in Table 139. The interrupt appears as an active low on the INTB pin in the microprocessor interface. ...

Page 141

... IDT IDT88K8483 PMON Buffer M-T Overflow Indication Register Read / Field Bits Write OVERFLOW[31:0] R/W 0:0-3:7 Table 142 PMON Buffer M-T Overflow Indication Register (Block Base=0x0F00, Register Offset=0x04-0x05) There are 2 registers. PMON Buffer T-M Overflow Interrupt Control Register Read / Field Bits Write OVF_EN[31:0] R/W 0:0-3:7 Table 143 PMON Buffer T-M Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x06-0x07) There are 2 registers ...

Page 142

... IDT IDT88K8483 PMON Buffer Overflow Source Register Read / Field Bits Write TM_OVF R 0:0 MT_OVF R 0:1 Table 145 PMON Buffer Overflow Source Register (Block Base=0x0F00, Register Offset=0x0A) PMON T-M Inactive Transfer LP Field Register Read / Field Bits Write LP R 0:0-0:7 Table 146 PMON T-M Inactive Transfer LP Field Register (Block Base=0x0F00, Register Offset=0x0B) ...

Page 143

... IDT IDT88K8483 PMON M-T Illegal SOP Event LID Field Register Read / Field Bits Write LID R 0:0-0:5 Table 150 PMON M-T Illegal SOP Event Field Register (Block Base=0x0F00, Register Offset=0x0F) PMON M-T Illegal EOP Event LID Field Register Read / Field Bits Write LID R 0:0-0:5 Table 151 PMON M-T Illegal EOP Event Field Register (Block Base=0x0F00, Register Offset=0x10) ...

Page 144

... IDT IDT88K8483 PMON Per LID Counter Table Register Length Offset 6n+1 24 0x6n+2 24 0x6n+3 24 0x6n+4 24 0x6n+5 Note: (1) In the register offset column ‘n’ refers to the LID number, with n between 0 and 63. The register address of the counter for a partic- ular LID is derived from the offset address using the equation shown in the register offset column and adding it to the block_base. ...

Page 145

... IDT IDT88K8483 Miscellaneous Registers PMON Timebase Control Register Read / Field Bits Write INTERNAL R/W 0:0 TIMER R/W 0:1 MANUAL R/WC 0:2 PMON Timebase Control Register Table 156 Manual Bit PMON 1ms Timer Register Read / Field Bits Write PERIOD R/W 0:0-2:1 Table 158 GPIO Direction Register Read / Field ...

Page 146

... IDT IDT88K8483 GPIO Level Register Read / Field Bits Write LEVEL R/W 0:0 GPIO Level Register (Block Base=0x8B00, Register Offset=0x13-0x15) Table 160 There are 3 registers. GPIO Link Table Read / Field Bits Write ADDRESS R/W 0:0- 1:7 BIT R/W 2:0- 2:4 REFLECT_EN R/W 2:5 GPIO Link Table (Block Base=0x8B00, Register Offset=0x16-0x18) Table 161 There are 3 registers ...

Page 147

... IDT IDT88K8483 Electrical and Thermal Specification Absolute Maximum Ratings Parameter Core Digital Supply Voltage I/O Digital Supply Voltage for LVDS I/O Digital Supply Voltage for HSTL I/O Digital Supply Voltage for LVDS I/O Digital Supply Voltage for HSTL I/O Digital Supply Voltage for LVTTL Analog Supply Voltage ...

Page 148

... IDT IDT88K8483 Parameter Reference for Termination I/O Reference for LDVS I/O Reference for HSTL Thermal Characteristics Parameter Maximum Power Dissipation total Maximum Power Dissipation of core Maximum Power Dissipation of each LVDS SPI-4 Interface I/O Maximum Power Dissipation of HSTL I/O (Memory Interface) Power Dissipation of LVTTL I/O Maximum Power Dissipation of Analog circuits ...

Page 149

... IDT IDT88K8483 DC Characteristics Parameter CMOS I/O Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage Schmitt Trigger Input - Low-Level Voltage Schmitt Trigger Input - High-Level Voltage I/O Off State Leakage Current Pull-Up Resistor in Input/Bidirectional I/O Pull-Down Resistor in Input/Bidirec- tional I/O LVTTL I/O Low-Level Input Voltage ...

Page 150

... IDT IDT88K8483 Parameter Differential Output Short Circuit Cur- rent HSTL I/O Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage AC Characteristics Parameter Clock Interface. Reference clock (SPI4M_RCLK, SPI4B_RCLK, SPI4A_RCLK) frequency Reference clock Duty cycle Reference clock PPM Reference clock frequency ...

Page 151

... IDT IDT88K8483 Parameter DCLK clock duty cycle SCLK clock duty cycle Fall time (20%, 80%) Rise time (20%, 80%) Differential Skew ( DCLK and SCLK peak to peak Jitter DAT and CTL peak to peak Jitter Clock-to-Output Propagation delay. This value 2 is programmable. SPI-4 Interface LVTTL. ...

Page 152

... IDT IDT88K8483 Parameter MCU Interface - Motorola mode - non multiplexed bus (MPM=0). Write Cycle. . Access p.155 Internal master clock (MCLK) frequency (defined by the main clock generator) Write cycle time Valid DSB width Delay from DSB to valid write signal R/WB to DSB hold time Delay from DSB to Valid Address ...

Page 153

... IDT IDT88K8483 Parameter SCLK Frequency Min. /CS High Time /CS Setup Time /CS Hold Time Clock Disable Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Output Delay Output Disable Time JTAG Interface. Figure 54 JTAG Interface p.158 TCK frequency TCK duty cycle ...

Page 154

... IDT IDT88K8483 K /K tKWV tKAV / D00 tKDV tKDV / D01 D10 D11 Figure 46 Auxiliary Interface - QDR-II / Generic - Write Access tKRV tKAV A Figure 47 Auxiliary Interface - QDR-II / Generic - Read Access 154 of 162 Q00 Q01 tQHD tQVD October 20, 2006 ...

Page 155

... IDT IDT88K8483 Figure 48 MCU Interface - Motorola Mode - Read Access ...

Page 156

... IDT IDT88K8483 CSB+_RDB A[x:0] Read[7:0] Note: WRB should be tied to high WRB+CSB A[x:0] Write[7:0] Note: RDB should be tied to high tRC tRDW tAV Valid Address tPRD Figure 50 MCU Interface - Intel Mode - Read Access tRC tRDW tAV Valid Address tDV Figure 51 MCU Interface - Intel Mode - Write Access ...

Page 157

... IDT IDT88K8483 A_ESCLK A_ESCLK VDDT33 DAT2 DAT1 DAT0 _L_P _L_N A A_ESTA_ A_ESTA_ VSS VSS DAT3 ADR5 WRB L_P[1] L_N[1] B A_ESTA_ A_ESTA_ DAT6 DAT5 DAT4 ADR3 RDB L_P[0] L_N[0] C A_ESCLK A_ESTA_ DAT7 ADR2 ADR4 INTB CSB _T T[1] D A_ESTA_ ADR0 ...

Page 158

... IDT IDT88K8483 /CS SCLK SDI High Impedance SDO TCK TDI TMS TDO tCSS tCLH tCLL tDIH tDIS Valid Input t PD Valid Output Figure 53 Serial Peripheral Interface t tStdi Htdi tStms t Htms Figure 54 JTAG Interface 158 of 162 tCSH tCLD tCSD tDF High Impedance t PDO ...

Page 159

... IDT IDT88K8483 Mechanical data Figure 55 BR 672 FCBG Package Outline, RoHS compliant 159 of 162 October 20, 2006 ...

Page 160

... IDT IDT88K8483 Document Revision History The document revision history is described in Table 169. Issue Date 1.0 10/20/2006 General Release Description Table 169 Document Revision History 160 of 162 October 20, 2006 ...

Page 161

... IDT IDT88K8483 Ordering Information The ordering information is described in Table 170. Device Code IDT88K8483BRI IDT88K8483 SPI-4 Exchange, Industrial temperature, RoHS 6 IDT88K8483BLI IDT88K8484 SPI-4 Exchange, Industrial temperature, RoHS 5 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 Product Table 170 Ordering Information ...

Page 162

... IDT IDT88K8483 162 of 162 October 20, 2006 ...