IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 43

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Bit alignment
eliminate bit errors by providing adequate set-up and hold time margins.
responsible for an edge transition histogram for each lane (lane is defined as a deferential pair of data, control or status signals). The data is sampled
by 10-phased-shifted clock during each clock cycle. Each 2 consecutive sampled values are XORed and accumulated during a fixed observation
window to generate transition edge histogram.
process is indicated by the BUSY field in the
launched. The BUSY field is auto cleared to 0 when the measure is finished. The received bit stream is selected from the 10 samples. The tap selec-
tion is made automatically and is available in the TAP_SEL field in the
Register (p. 117)
De-skew
of range offset between lines is provided. If the skew is more than 2 bits, then the I_DSK_OOR field in the
set. The I_DSK_OOR field is cleared when the offset is in range.
Receive State Machine
number of consecutive error-free DIP-4 are detected. The number is configured by using the
machine stays in OUT_OF_SYNCH state if the interface is not enabled.
captured by the
nization status is fed to status channel generation logic for handshaking.
IDT IDT88K8483
The bit alignment block is responsible for data and clock alignment. The bit alignment allows the clock to be used for correct data sampling and
The alignment selection is programed by AUTO_ALIGN field in the
The measurement histogram is triggered by writing to the LANE field in the
The bit alignment sequence automatically carried out in the device as follows:
- Write lane number in the LANE field in the
- Poll the BUSY field in the
- Write the selected Tap value to TAP field in the
The De-skew block is responsible for alignment between the data signals. The De-skew block can de-skew +/-1bit. For diagnose purpose, an out
The ingress data channel has 2 states, IN_SYNCH and OUT_OF_SYNCH. The machine transitions from OUT_OF_SYNCH to IN_SYNCH if a
The status of the synchronization is indicated by I_SYNCV field in the
PMON Event Interrupt Indication Register (p.
which indicates the counter value. The counter value is used to select the tap.
Skew control
alignment
Bit
SPI-4 Histogram Measure Status Register (p.
Deskew
SPI-4 Histogram Measure Status Register (p.
SPI-4 Histogram Measure Launch Register (p.
SPI-4 Bit Alignment Result Register (p.
Figure 15 SPI-4 Ingress Block Diagram
136). An interrupt is generated if interrupt options is enabled. The data channel synchro-
Rx machine
generation
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status
SPI-4 Bit Alignment Result Register (p.
SPI-4 Ingress Automatic Alignment Control Register (p.
SPI-4 Ingress Status Register (p.
117). If BUSY is 0, then read the C[n] field in the
SPI-4 Histogram Measure Launch Register (p.
Locker
status
118).
117). The BUSY field is set to 1 when a measurement is
117).
SPI-4 Ingress Configuration Register (p.
SPI-4 Ingress Status Register (p. 108)
PFP
108). Any transition on I_SYNCV will be
118).
SPI-4 Histogram Counter
117). The measurement
October 20, 2006
109). The device is
106). The
is