IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 45

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

after last ‘11’ framing pattern.
and excluding the calendar selection word.
buffer fill level. See
length=I_CAL_LEN+1. In LVTTL mode, the I_CAL_LEN field can be programmed to any value. In LVDS mode, the I_CAL_LEN field must be
programmed to 4n-1 (n is an integer).
Output Skew
to 0.9 clock cycles with a resolution of 0.1 clock cycle. The data outputs can be skewed over a range of 0 to 0.3 clock cycle with a resolution of 0.1
clock cycle. The skews are controlled by the output delay registers.
Diagnostics Features
SPI4M_IDCLK_P, and SPI4M_IDCLK_N) is monitored. If there is no transition on IDCLK in a 2048 MCLK hopping window, then the DCLK_AV field in
the
PMON captures this event.
unavailable event, and forwards the event to PMON.
DIP_E_NUM field in the
set to 1, it triggers error insertion using the I_DIP_NUM field value. The I_ERR_INS field is self cleared when the correct number of errors is gener-
ated. The I_DIP_NUM field value is not changed by device.
Ingress Diagnostics Register (p. 109)
set to 1.
The maximum port buffer fill level is configured by using the FILL_MAX field in the
SPI4 egress Data Channel
output skew is per lane controllable. The status channel does bit alignment and de-skew in LVDS mode. The device receives status frame for control-
ling the data path flow. In packet mode, the TX machine must transmit a complete packet before it starts a transfer for another logical port.
IDT IDT88K8483
If the I_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after the last ‘11’ framing pattern.
If I_CSW_EN is set to 1, and I_DIP_CSW is set to 1, then the DIP-2 is computed over calendar selection word and all preceding status indications
If I_CSW_EN is set to 1, and I_DIP_CSW is set to 0, then the DIP-2 is computed over all preceding status indications after last ‘11’ framing pattern
The starving, hungry or satisfied indication for each status word for each logical port is based on the status from the PFP and the SPI-4 ingress port
The calendar length is configured by the I_CAL_LEN field in the
The LVDS output lane skew is adjustable in order to provide greater flexibility for board layout. The clock outputs can be skewed over a range of 0
- Ingress data channel clock detect. The ingress data clock IDCLK (SPI4A_IDCLK_P, SPI4A_IDCLK_N, SPI4B_IDCLK_P, SPI4B_IDCLK_N,
- Ingress port buffer unavailable. If there is more data but no port buffer available, then the device discards the data, generates a SPI_4 port buffer
- DIP-2 error insertion. A number of consecutive (less then 16) DIP-2 errors can be generated. The number of errors is configured by the
- Force continuous training. The status channel generates continuous training pattern in LVDS protocol if I_FORCE_TRAIN field in the
- Ingress port buffer fill level. The ingress port buffer fill level is indicated in the FILL_CURR field in the
The SPI4 egress interface has data channel and status channel. The data channel carries transfers, and the status channel carries status. The
SPI-4 Ingress Status Register (p. 108)
SPI-4 Ingress WATERMARK Register (p.
SPI-4 Ingress Diagnostics Register (p.
is set to 1. The status channel generates a continuous ‘11’ pattern in LVTTL protocol if I_FORCE_TRAIN field is
is cleared to 0. The DCLK_AV flag transition from 1 to 0 generates an event towards the PMON, and the
111).
109). When the I_ERR_INS field in the
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SPI-4 Ingress Calendar 0 Configuration Register. (p. 107)
SPI-4 Ingress Training to out of sync threshold Register (p.
SPI-4 Ingress Diagnostics Register (p. 109)
SPI-4 Ingress Fill Level Register (p.
October 20, 2006
while calendar
111).
SPI-4
110).
is