IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 33

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Functional Description
multi-service switches. The SPI-4 interface is defined by the Optical Internetworking Forum.
multi-gigabit MACs, framers and switch fabric interface devices. A set of HSTL pins may be configured as a packet bus to an FPGA or as a QDR-II
memory bus. The FPGA interface can be used to reduce the unnecessary overhead generated in the FPGA by a SPI-4 standard interface. QDR-II
memory can be added as an expansion of internal memory provided in the device.
DATA PATH
M ingress to SPI-4A and SPI-4B egress path. SPI-4 burst sizes are separately configurable for each physical port. Data enter in bursts on a SPI-4
ingress interface and are sent to the SPI-4 ingress port buffers. The bursts are mapped to a SPI-4 address and stored in the buffer segment pool by
the packet fragment processor (PFP). The PFP forward the data to the SPI-4 Egress Port Buffer. The content of the Egress Port buffer is transferred
to the SPI-4 egress interface and transmitted out in burst.
SPI-4 interface has the ability to perform a per-LP loopback. In addition, the SPI-4A and SPI-4B interfaces can transfer packet bursts on a per-LP
basis. All the SPI-4 interfaces can transfer packet bursts to the FPGA interface on a per-LP basis.
Data Structure
there is one PFP. Each PFP has 508 segments, and each segment has 256 bytes as shown in
user can program the LID allocation in the PFP to allocate the 508 segments to the LIDs that will be active. For example, the user can have 64 LIDs,
and allocate 7 segments (1,792) bytes to each LID as shown in
PFP Structure
IDT IDT88K8483
The IDT88K8483 device is a three port SPI exchange device intended for use in Ethernet transport, SONET/SDH line cards, security firewalls, and
The device can be used to provide rate adaptation, switching, aggregation and fragment to packet conversion between network processor units,
Each SPI-4 ingress LP (logical port) can be mapped through LID (Logical Identifier) to each one of the SPI-4 egress LPs
There are 4 PFPs (Packet Fragment Processor) in the device - one per each port and direction. For example, for SPI-4A ingress to SPI-4M egress
In addition to the data path described above, there are additional datapaths among the SPI-4 ports, FPGA interface, and microprocessor. Each
In normal operation, there are two paths through the IDT88K8483 device: the SPI-4A or SPI-4B ingress to SPI-4M egress path, and the SPI-4
Interface
Ingress
SPI-4
Ingress
Buffer
SPI-4
Port
IDT88K8483
Figure 2 General Data Path
Figure 4 PFP Allocation Example
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Segment
Buffer
(PFP)
Pool
Egress
Buffer
SPI-4
Port
Figure 3 PFP Structure Example
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Interface
Egress
SPI-4
October 20, 2006
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