IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 151

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

IDT IDT88K8483
DCLK clock duty cycle
SCLK clock duty cycle
Fall time (20%, 80%)
Rise time (20%, 80%)
Differential Skew (P to N)
DCLK and SCLK peak to peak Jitter
DAT and CTL peak to peak Jitter
Clock-to-Output Propagation delay. This value
is programmable.
SPI-4 Interface LVTTL.
SCLK clock frequency
SCLK clock duty cycle
Input Setup time
Input hold time
Clock-to-Output Propagation delay:
Auxiliary Interface - QDR-II / Generic.
Auxiliary interface clock frequency
Auxiliary interface clock period (1/f
Auxiliary interface clock duty cycle
Clock to write valid
Clock to address valid
Clock to data valid
Clock to read valid
Echo clock to data setup
Echo clock to data hold
MCU Interface - Motorola mode - non multiplexed bus (MPM=0). Read Cycle.
Access p.155
Read cycle time
Valid DSB+CSB width
Delay from DSB to valid read signal
R/WB to DSB hold time
Delay from DSB to Valid Address
Address to DSB hold time
DSB to valid read data propagation delay
Delay from read data active to high Z
Recovery time from read cycle
Parameter
2
.
aux
)
Figure 46 Auxiliary Interface - QDR-II / Generic - Write Access p.154
I
I
T
faux
T
tKWV
tKAV
tKDV
tKRV
tQVD
tQHD
F
RISE
SKEW1
ALL
Symbol
Table 168 AC Characteristics (Part 2 of 4)
tRecovery
tRWV
tRWH
tADH
tPRD
tDAZ
tDW
tRC
tAV
151 of 162
TIA/EIA-644
TIA/EIA-644
Conditions
Figure 48 MCU Interface - Motorola Mode - Read
133
7.51
40
0.2T
0.2T
0.2T
0.2T
-0.4
-0.4
tDW+ tRe-
covery
tRWH
19.44
Min
tPRD
300
300
0.5
45
45
40
4T
2
5
Typ
50
50
50
1
200
5
60
0.3T
0.3T
0.3T
0.3T
2Tmax-2
2Tmax-2
Max
112.5
0.24
500
500
0.1
0.6
1.2
55
55
50
60
6T
10
and
October 20, 2006
1
Figure 47
MHz
ns
%
“T” is in ns
“T” is in ns
“T” is in ns
ns
ns
“T” is in ns
Unit
MHz
ps
ps
ps
UI
UI
UI
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
.