IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 30

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

IDT IDT88K8483
QDR_D[35:0]/
G_ECTL[3:0],
G_EDAT[31:0]
QDR_Q[35:0]/
G_ICTL[3:0],
G_IDAT[31:0]
QDR_RB
QDR_WB
QDR_K / G_ECLKP
QDR_KB / G_ECLKN
QDR_CQ / G_ICLKP
QDR_CQB / G_ICLKN
QDR_VREF / G_VREF
QDR_IMP / G_IMP
Microprocessor Interface
ADR[5:0]
DAT[7:0] / SDO
Symbol
1
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
Reference
Reference
Type
Analog
CMOS
CMOS
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
2
QDR_D[35:0] is QDR-II Output Data Bus. This bus is used to transfer
the data to the QDR-II / FPGA devices. It is driven out on the rising
edge of K and K clocks during write operation.
G_ECTL[3:0] is Generic Interface Egress Control Bus.
G_EDAT[31:0] is Generic Interface Egress Data Bus.
QDR_Q[35:0] is QDR-II Input Data Bus. This bus is used to transfer
data from the QDR-II / FPGA devices. It is sampled on the rising edge
of K and K clocks during read operation.
G_ICTL[3:0] is Generic Interface Ingress Control Bus.
G_IDAT[31:0] is Generic Interface Ingress Data Bus.
QDR_RB is QDR-II Read Control. This active low signal is driven out on
the rising edge of K clock. When it active, a read operation is initiated.
When it deasserted, the read port is deselected.
QDR_WB is QDR-II Write Control. This active low signal is driven out
on the rising edge of K clock. When it asserted, a write operation is initi-
ated. When it deasserted, the write port is deselected.
QDR_K is QDR-II Positive Output Clock. The rising edge of QDR_K is
used to capture input data to the device and to drive out data from the
device.
G_ECLKP is Generic Interface Positive Egress Clock.
QDR_KB is QDR-II Negative Output Clock. The rising edge of QDR_KB
is used to capture input data to the device and to drive out data from the
device.
G_ECLKN is negative Generic Interface Egress Clock.
QDR_CQ is QDR-II Synchronous Positive Input Clock. The rising edge
of QDR_CQ is tightly matched to the data inputs and can be used as a
data valid indication.
G_ICLKP is Generic Interface Positive Ingress Clock.
QDR_CQB is QDR-II Synchronous Negative Input Clock. The rising
edge of QDR_CQB is tightly matched to the data inputs and can be
used as a data valid indication.
G_ICLKN is Generic Interface Negative Ingress Clock.
QDR_VREF is 0.75 Reference Voltage Input. This static input is used to
set reference level for HSTL inputs and outputs as well as AC measure-
ment points. This pin should be connected to V
G_VREF is 0.75 Reference Voltage Input. This pin should be con-
nected to V
QDR_IMP is Reference Input. This signal must be connected via an
external pull-down 100 OHM resistor to VSS.
G_IMP is Reference Input. This signal must be connected via an exter-
nal pull-down 100 OHM resistor to VSS.
ADR[5:0] is Microprocessor Address Bus. This bus is used to transfer
the address from the micro-controller.
DAT[7:0] is Microprocessor Data Bus. This bus is used to transfer the
data between the device and the microprocessor.
SDO (DAT[0]) is Serial Peripheral Interface (SPI) data.
Table 2 Pin Description (Part 3 of 5)
DDH15
30 of 162
/2.
Function
DDH15
/2.
Comments
October 20, 2006