IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 74

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Ensure that the buffer has sufficient drive capability to supply all loads. When using a buffer to drive any of the JTAG TAP pins, it may be necessary to
include an external resistor to ensure the pin is set to the correct state when the buffer is idle. Thus, TRSTB should have an external resistor to ground
when driven by an external buffer and TMS and TCK should each have an external pull-up.
GPIO
Register (p.
of any bit which is selected from the indirect access space if enabled. A bit in the indirect access space can be selected by the ADDRESS and BIT
fields in the
the unused GPIO signals to an FPGA or microprocessor pins for debugging purpose.
Power Supply
tion Example p.75.
p.75.
IDT IDT88K8483
The JTAG instructions are described in
The device has 3 general purpose input/output pins. The pins’ direction is independently controlled by the DIR_OUT field in the
The IDT88K8483 Power Supplies can be generated as shown in the design example in
1. Connect the
2. Connected together the
3. Separate the
4. Generate the
5. Generate the V
Version
0
GPIO Link Table (p.
145). The logical level on the pins is controlled by the LEVEL field in the
V
Instructions
V
V
DDA25
DDC12
DDL25
USERCODE
TT075
RUNBIST
SAMPLE
EXTEST
IDCODE
BYPASS
The IDT88K8483 system should have the following:
CLAMP
HIGHZ
signals through filter to The
/ V
signals and
signals from
DDH25
V
DDH25
146). A bit can be enabled by the REFLECT_EN field in the
signals from
Part Number
signals and the
V
V
DDL12
0x4af
DDH15
Table
signals.
signals.
V
DDT33
11. The JTAG ID information is described in
V
V
DDL25
signals.
DDH25
Table 11 JTAG Instruction Code
signals.
/
V
Instruction Codes
DDL25
Table 12 JTAG ID
74 of 162
signals as described in
000
001
100
011
010
110
101
111
Manufacture ID
0x33
GPIO Level Register (p.
GPIO Link Table (p.
Figure 41 IDT88K8483 Power Supply Genera-
Figure 42 IDT88K8483 VDDA25 Filter Circuit
Table
Test the function to other devices
Used to connect the identification register
Set outputs to Hi-Z state
Clamp the output latches
Sample all the inputs and outputs
BIST
User code
Used to bypass the device
12.
Function Description
146). The LEVEL field reflects the status
146). IDT recommends to connect all
Fixed
1
October 20, 2006
GPIO Direction