IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 103

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Secondary Interrupt COMMON Enable Register
TIMEBASE_EN
INDIRECT_ACC_EN
I_FIFO_READY_EN
I_FIFO_OFLOW_EN
O_FIFO_MSG_EN
SOC_EN
10ms_EN
Note: Writing a 1 to any field in this register, causes an interrupt to be generated based on the occurrence of that particular event indicated in the corresponding
field in
IDT IDT88K8483
Field
Table
50. The interrupt appears as an active low on the INTB pin in the microprocessor interface.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read /
Write
0:0
0:1
0:2
0:3
0:4
0:5
0:6
Table 51 Interrupt Secondary COMMON Enable Register (register_offset=0xf)
Bits
1
1
1
1
1
1
1
Length
0
0
0
0
0
0
0
Reset
State
103 of 162
This field enables an interrupt to be generated if an event is captured in “TIMEBASE”
field in the
appears as an active low on the INTB pin in the microprocessor interface.
0: Disable.
1: Enable.
This field enables an interrupt to be generated if an event is captured in
“INDIRECT_ACC” field in the
(p.
interface.
0: Disable.
1: Enable.
This field enables an interrupt to be generated if an event is captured in
“I_FIFO_READY” field in the
(p.
interface.
0: Disable.
1: Enable.
This field enables an interrupt to be generated if an event is captured in
“I_FIFO_OFLOW” field in the
(p.
interface.
0: Disable.
1: Enable.
This field enables an interrupt to be generated if an event is captured in O_FIFO_MSG
field in the
appears as an active low on the INTB pin in the microprocessor interface.
0: Disable.
1: Enable.
This field enables an interrupt to be generated if an event is captured in “SOC” field in
the
as an active low on the INTB pin in the microprocessor interface.
0: Disable.
1: Enable.
This field enables an interrupt to be generated if an event is captured in “10ms” field in
the
as an active low on the INTB pin in the microprocessor interface.
0: Disable.
1: Enable.
102).The interrupt appears as an active low on the INTB pin in the microprocessor
102).The interrupt appears as an active low on the INTB pin in the microprocessor
102).The interrupt appears as an active low on the INTB pin in the microprocessor
Secondary Interrupt COMMON Indication Register (p.
Secondary Interrupt COMMON Indication Register (p.
Secondary Interrupt COMMON Indication Register (p.
Secondary Interrupt COMMON Indication Register (p.
Secondary Interrupt COMMON Indication Register
Secondary Interrupt COMMON Indication Register
Secondary Interrupt COMMON Indication Register
Description
102).The interrupt appears
102).The interrupt appears
October 20, 2006
102).The interrupt
102).The interrupt