IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 57

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Flow Control Mode 2 - Buffering
mode. In this option, the EBC[2:0] field in the
Figure 25 QDR-II FIFOs Allocation Example For Buffering Option
Mode Control Registers (p. 123)
field in the
flow control mode 2 should be enabled in the PFP by setting to 1 the EBP_EN field in the
device fixes the Second Free Segments (Second Free Segments) to 6 as shown in
Option
are enough free segments, so the FIFO status is starving, and the QDR-II is sending starving status to the PFP. When the number of free segments is
less than EBP_THR (for example 100 segments), the QDR-II FIFO status is changed to hungry, and the QDR-II starts sending hungry status to the
PFP. When the number of free segments is less than the Second Free Segments (6 segments), the QDR-II FIFO status is changed to satisfied, and
the QDR-II starts sending satisfied status to the PFP.
IDT IDT88K8483
Framer
In the buffering option the IDT88K8483 gets the data in interleaved mode or in packet mode and it sends the data in packet mode or in interleave
In buffering option, the PFP and the QDR-II should be programed to packet mode by setting to 1 the PKT_MODE field in the
There are three status options per FIFO in the QDR-II: starving hungry and satisfied. In the QDR-II for LP0 (for example), in normal operation there
p.58.
Auxiliary Early Backpressure Threshold Register (p. 131)
status
data
Interface
Ingress
SPI-4
Interleaved
Channels
and the PKT_MODE field in the
Ingress
Buffer
SPI-4
Port
Figure 25 QDR-II FIFOs Allocation Example For Buffering Option
(p. 129)
Figure 24 Flow Control Mode 1 Application Example
QDR-II (8K segments, 2M bytes, 16M bits)
should be configured to the number of FIFOs in the QDR-II (64, 32, 16, 8 or 4) as described in
508 segments
127K bytes
Ingress
PFP
Auxiliary Packet Mode Configuration Register (p.
57 of 162
should be programmed with the early back-pressure threshold value. Also, the
LID 63
LID 1
LID 0
8K segments
Reassembly
2M bytes
.
.
.
QDR
p.57. Each FIFO gets the same amount of buffer size.
Non-Interleaved
Channels
Figure 26 QDR-II Flow Control Example For Buffering
508 segments
127K bytes
128 segments / 32K bytes
PFP Egress Packet Mode Control Registers (p.
Egress
PFP
Egress
Buffer
SPI-4
Port
131). In addition, the EBP_THR
Interface
Egress
SPI-4
October 20, 2006
PFP Egress Packet
status
data
123). The
NP