IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 135

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

LID Register
Synchronization Register
Bit Error Insertion Register
PMON Registers
LID
IDT IDT88K8483
SYNCV
SYNCI
Note: (1)The out of sync status can be due to any one of 3 reasons.
ERROR_INS
(2) A transition from out of sync to in sync is caused by 48 consecutive error free bits.
(3) In the in sync state, each mismatched bit will generate a bit error event and will be forwarded to PMON.
Field
Field
Field
a) Resetting the device.
b) If field “DEN” in Enable Control Register (p. 133) is 0.
c) If excessive errors between regenerated sequence from the received data and received sequence.
R/W
R/W
R/W
R/W
Read/
Write
Read/
Write
Read/
Write
Table 138 Bit Error Insertion Register (Block Base=0x0B00, Register Offset=0x08)
Table 137 Synchronization Register (Block Base=0x0B00, Register Offset=0x07)
0:0
0:1
0:0
0:0 - 0:5
Bits
Table 136 LID Register (Block Base=0x0B00, Register Offset=0x06)
Bits
Bits
1
1
1
Length
6
Length
Length
135 of 162
0
0
0
Reset
State
0
Reset
State
Reset
State
This field indicates the synchronization status of the PRBS detector.
0: Out of sync.
1: In sync.
This field captures any transaction in the field SYNCV.
0: No change.
1: Change in state from out of sync to in sync or vice-versa.
Write 1: Clear
This field is used to insert a single bit error into the PRBS
generator.
0: Bit error is not inserted.
1: 1 bit error is inserted After the error is inserted, it auto clears.
This field indicates the LID which is selected to transfer the
PRBS packet burst.
Description
Description
Description
October 20, 2006