IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 79

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Indirect Read and Write Operation:
IDT IDT88K8483
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– The OBC reads the BUSY flag in the Microprocessor Indirect Access Control Register (p. 93). It proceeds only when the flag is cleared.
– The indirect WRITE access operation is triggered by a write operation in the indirect access control register. This is achieved by setting field
– The process sets the BUSY flag in the indirect access control register immediately and verifies the indirect address.
– When the address is out of bounds, no internal memory is accessed and the BUSY flag is cleared.
– When the address is within bounds the indirect write operation is achieved as soon as possible.
– The BUSY flag is cleared as soon as the Write operation is completed and the address is auto incriminated
– The ERROR field in the Microprocessor Indirect Access Control Register (p. 93) indicates an errorcode.Correct operation returns ERROR =
– The indirect READ access operation is triggered by a read operation to the indirect access control register. This is achieved by setting field
– The process sets the BUSY flag in the indirect access control register immediately and verifies the indirect address.
– When the address is out of bounds, no internal memory is accessed and the BUSY flag is cleared. Also the indirect access data regis-
– When the address is within bounds the indirect read operation is achieved as soon as possible.
– The BUSY flag is cleared as soon as the Read operation is completed and the address is automatically incremented.
– The ERROR field in the Microprocessor Indirect Access Control Register (p. 93) indicates an error code. Correct operations return ERROR
Indirect Write Access Operation
Indirect Read Access Operation
RWN to 0 in the Microprocessor Indirect Access Control Register (p. 93).
0.
RWN to 1 in the Microprocessor Indirect Access Control Register (p. 93).
ters(p.85) are cleared.
= 0.
direct access
indirect access
process
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Figure 45 Indirect access module
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indirect access
October 20, 2006