IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 29

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

IDT IDT88K8483
SPI4A_ID[15:0]_P
SPI4B_ID[15:0]_P
SPI4M_ID[15:0]_P
SPI4A_ID[15:0]_N
SPI4B_ID[15:0]_N
SPI4M_ID[15:0]_N
SPI4A_IDCLK_P
SPI4B_IDCLK_P
SPI4M_IDCLK_P
SPI4A_IDCLK_N
SPI4B_IDCLK_N
SPI4M_IDCLK_N
SPI4A_ICTL_P
SPI4B_ICTL_P
SPI4M_ICTL_P
SPI4A_ICTL_N
SPI4B_ICTL_N
SPI4M_ICTL_N
SPI4A_ISTA[1:0]_P
SPI4B_ISTA[1:0]_P
SPI4M_ISTA[1:0]_P
SPI4A_ISTA[1:0]_N
SPI4B_ISTA[1:0]_N
SPI4M_ISTA[1:0]_N
SPI4A_ISCLK_P
SPI4B_ISCLK_P
SPI4M_ISCLK_P
SPI4A_ISCLK_N
SPI4B_ISCLK_N
SPI4M_ISCLK_N
SPI4A_ISTA_T[1:0]
SPI4B_ISTA_T[1:0]
SPI4M_ISTA_T[1:0]
SPI4A_ISCLK_T
SPI4B_ISCLK_T
SPI4M_ISCLK_T
SPI4A_BIAS
SPI4B_BIAS
SPI4M_BIAS
SPI4A_VREF
SPI4B_VREF
SPI4M_VREF
SPI4A_LVDSSTA
SPI4B_LVDSSTA
SPI4M_LVDSSTA
QDR-II Interface / Generic Interface (Auxiliary Interface)
QDR_A[17:0]
Symbol
1
I/O
O
O
O
O
O
I
I
I
I
Schmitt Trigger
Pull-down
Type
LVTTL
Pull-up
LVTTL
Pull-up
Analog
Analog
CMOS
LVDS
LVDS
LVDS
LVDS
LVDS
HSTL
2
Ingress Data Bus. This data bus is used to carry ingress payload data
and in-band control words.
Ingress Data Clock. This clock is associated with the ingress data bus
(ID) and the control signal (ICTL).
Ingress Control. This signal is high when a control word is present on
the ingress data bus (ID) and it is low otherwise.
Ingress FIFO Status LVDS. These signals are used to carry ingress
round-robin FIFO status information, along with associated error detec-
tion and framing.
Ingress Status Clock LVDS. This clock is associated with the ingress
FIFO status signals (ISTA).
Ingress FIFO Status LVTTL. These signals are used to carry ingress
round-robin FIFO status information, along with associated error detec-
tion and framing.
Ingress Status Clock LVTTL. This clock is associated with the ingress
FIFO status signals (ISTA_T).
BIAS. This signal must be connected via an external pull-down 1% 3KΩ
resistor to VSS.
REF. These signals are reference for LVDS. These signals should be
connected to VDDL12.
Status Channel Control. This signal controls the status signal I/O type.
A hardware reset or software reset must be perform after changing the
level of this signal. 1 - LVDS status. 0 - LVTTL status.
QDR_A[17:0] is QDR-II Address Bus. This bus is used to transfer the
address to the QDR-II / FPGA devices. It is driven out on the rising
edge of K and K clocks during write or read operation.
Table 2 Pin Description (Part 2 of 5)
29 of 162
Function
RDAT[15:0]
RDCLK
RCTL
RSTAT[1:0]
RSCLK
RSTAT[1:0]
RSCLK
Comments
October 20, 2006
TDAT[15:0]
TDCLK
TCTL
TSTAT[1:0]
TSCLK
TSTAT[1:0]
TSCLK