IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 106

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Interface Enable Register
SPI-4 Ingress Configuration Register
SPI4_EN
SPI4_PDN
I_INSYNC_THR
I_CLK_EDGE
I_LOW
Reserved
I_OUTSYNC_THR
Note: Please refer to Figure 16 for an illustration of out of sync and in sync state.
IDT IDT88K8483
Note:
Field
Field
Table 58
(1) The SPI4 interface has to be configured before enabling the interface
R/W
R/W
R/W
R/W
R/W
R
R/W
Read /
Read /
Table 57
Write
Write
SPI-4 Ingress Configuration Register (Block Base=0x0300, Register Offset=0x01)
SPI-4 Interface Enable Register (Block Base= 0x0300, Register Offset=0x00)
0:0
0:1
0:0-0:4
0:7
1:0-1:3
0:5
0:6
Bits
Bits
1
1
5
1
1
1
4
Length
Length
0
0
0x1F
1
1
0
0xF
Reset
Reset
State
State
106 of 162
This bit enables/disables the SPI-4 interface ingress path. The SPI-4 ingress path is
disabled during reset and while configuring the port and is then enabled for normal
use.
0: Disable.
1: Enable.
SPI4 interface power down mode.
0:Power up.
1:Power down or disable the SPI4 LVDS I/O, except the clock.
The number of consecutive error free DIP-4 that need to be detected before the
SPI-4 ingress data channel is synchronized. The actual number of error free DIP 4
that need to be detected is I_INSYNC_THR+1.
Indicates the active edge of the status clock in LVTTL mode.
0:The status information is output at the rising edge of the status clock.
1:The status information is output at the falling edge of the status
This bit should be set to ‘0’ or ‘1’depending on the frequency of the ingress status
clock output when the status channel is selected to run in LVDS mode (LVDS_STA
bit inTable 62 indicates a ‘1’)
0: ISCLK clock is higher than or equal to 200 MHz.
1: ISCLK clock is lower than 200 MHz.
Reserved bits.
Indicates the number of consecutive DIP4 errors that need to be detected before the
ingress data channel changes from in sync state to out of sync state
Description
Description
October 20, 2006
clock.