ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 126

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

16.5.3 Filtering the Noise on Input Signals
Input signals may be accompanied by unwanted noises
caused by the digital circuits they pass nearby. Optionally,
when converting slow changing signals in a noisy environ-
ment, a low pass filter (LPF) may be added externally. This
can be implemented simply by placing a low value capaci-
tor, C
off frequency of this LPF should be above the measured
signal frequency.
16.5.4 AD0-7 Multiplexing with PD0-7 Port
Analog input signals AD0-7 are multiplexed with digital input
signals PD0-7. These pins do not have internal pull-up re-
sistors and back-drive protection (see Section 16.5.1 on
page 125 for futher details).
Each pin function is selected by dedicated bits in the PDALT
Register (see Table 2-4 on page 26). If the voltage value on
the pins is between zero and the actual V
rent consumption is kept to a minimum, as follows:
For ESD protection reasons, it is not recommended to leave
these pins open. See Table 19-3 on page 133 for their char-
acteristics.
16.5.5 Calculating the Sampling Time
The sampling time is the period between input selection in
the multiplexer and the conversion start (i.e., hold point).
Figure 16-5 shows the schematic of the input and its equiv-
alent R-C circuit. The sampling time should be long enough
to guarantee the settling of the voltage on the sampling ca-
pacitor, C
held for the duration of the conversion. The R
(see Section 19.3.1 on page 134) values represent the input
path serial resistance and parallel capacitance. R
serial resistance of the multiplexer, Sample and Hold switch
and other parasitic resistors. C
tance of the input pin, pad, lead-frame, C
quired sampling time is determined by R
together with the input source resistance R
asitic capacitance C
ence for calculating the sample time. The DELAY bit of the
ADCCNT3 Register should be programmed accordingly.
Pins used as digital inputs (PD0-7, PDALT=00h):
If the CR16A core is not reading from the PDDIN Reg-
ister or the chip is in Idle mode, the input buffers of
port D are blocked.
Pins used as analog inputs, (AD0-7, PDALT=FFh):
If the chip is either in Active or Idle mode, the input im-
pedance of the pins is as defined in Table 19-5 on
page 134.
1
, on the divider output shown in Figure 16-2. The cut-
S
. The voltage on C
P
. Table 16-7 can be used as a refer-
S
should be stable before it is
AIN
Analog to Digital Converter (ADC) - January 1998
is the parallel capaci-
CC
SOURCE
S
/AV
AIN
, etc. The re-
AIN
CC
and C
and C
AIN
, the cur-
and par-
is the
AIN
AIN
126
.
Signal
Input
Figure 16-5. Analog Input Schematic Diagram
[pF]
27.5
C
50
Elements
5
External
P
V
V
Table 16-7. Recommended Sampling Time
IN
IN
R
R
S
C
[K ]
S
0.1
0.1
0.1
R
10
30
10
30
10
30
P
1
1
1
S
and Equivalent R-C Circuit
Sampling
Time [ns]
11400
3200
2220
7900
3350
110
900
210
430
15
25
45
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
R
(min) as function of ADC Clock
(1000 ns)
Number of ADC Clock Cycles
AIN
1 MHz
16
1
1
1
4
1
1
4
8
1
1
4
Analog
(DELAY of ADCCNT3)
MUX
8:1
500 KHz
(500 ns)
16
32
1
1
2
8
1
1
8
1
1
8
C
and Hold
Sample
AIN
C
www.national.com
s
250 KHz
(250 ns)
16
16
32
16
64
1
1
4
1
1
1
2