ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 43

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

3.3.7
The I/O expansion bus cycles enables you to implement the
functionality of on-chip I/O ports (when the pins of the on-
chip I/O ports are used to support IRD or Dev environment)
and/or additional ports, using off-chip external logic.
I/O expansion bus cycles access the off-chip I/O device us-
ing the following signals:
SELIO
Address lines A0-7
The RD and WR0-1 signals may be used.
I/O Expansion Bus Cycles
CLK
A0-18
SELIO
D0-15
RD
WR0-1
BST0-2
CLK
A0-18
SELx
SELy
D0-15
RD
WR0-1
BST0-2
(x
(y
y)
x)
Figure 3-13. I/O Expansion Bus Cycles (BCFG.EWR = 1)
T
T
Idle
Idle
Figure 3-12. Fast Read Bus Cycle
T1
Read
Fast
T1-2
Read
In
Bus Interface Unit (BIU)
T2
T1
Late Write
In
43
T
The design minimizes the off-chip logic required to imple-
ment the I/O ports. It is costly to implement a port with pins
individually configured for input or output. Implementing
ports which are input only or output only, reduces expenses.
I/O expansion bus cycle is not generated during an access
to a port register when:
I/O Expansion Read/Write Bus Cycle
These cycles are always preceded by a T
See Figure 3-13. The I/O zone is not burstable.
Idle
T2
Out
Any port pin is available on-chip
All port pins are inputs, and the port is being written.
T1
Cycle
Idle
T
Idle
Write
T2
Fast
Read
Out
T1-2
In
T3
T1
idle
clock cycle.
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