ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 164

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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B. Bootloader Description
B.1
The bootloader program resides in the 2K on-chip ROM of
the PC87570. It provides for an orderly transfer to the BIOS
program, which resides in off-chip Flash, after power-up or
reset. The bootloader program reads the configuration and
strap pin settings after reset, and combines this information
with the BIOS configuration block settings to determine in
which mode to set the PC87570 to access the External
Memory. A number of External Memory tests (one of which
may be user-defined) are performed to verify that the BIOS
Flash is not corrupt and that control is passed to the Key-
board BIOS program. If the BIOS is corrupt, the bootloader
program accepts commands from the secondary host inter-
face (64h), which can assist the main processor in reloading
the BIOS Flash memory.
B.2
The External Memory has two configuration blocks: the
System Configuration Block and the Keyboard Controller
(KBC) Header.
B.2.1
The System Configuration Block is used to help set up the
PC87570 for hardware implementation (including all mem-
ory zone access times, and the size and width of the Exter-
nal Memory) and with system information (including
signature and a pointer to the KBC Header). It resides at ab-
solute address 0004h - 001Fh of the External Memory. The
System Configuration Block definitions are:
Even though some configuration registers are only a single
byte wide,16 bits have been reserved for each entry.
4 Signature byte set to E3h
5 Signature byte set to 8Eh
6 Signature byte set to 1Ch (complement of first sig-
7 Signature byte set to 71h (complement of second
8 Length of System Configuration Block set to 22 (16h)
9 Reserved
10 Page Register
12 Pointer to start of KBC Header (2 bytes, absolute
14 Module Configuration Register (MCFG), only.
16 BIU Configuration Register (BCFG)
18 IO Zone Configuration Register (IOCFG)
20 Static Zone Configuration Register 0 (SZCFG0),
22 Base Memory (Boot ROM) Configuration Reg 1
24 PE Pins Alternate Function Enable Register
26 - 31 Reserved
OVERVIEW
CONFIGURATION BLOCKS
nature byte)
signature byte)
address)
CLKOE, EXIOE & A15E bits are used. Other bits
are set by the bootloader according to the strap op-
tions (only. TEST is set directly by the strap option)
BW set by configuration pin PH.3
(SZCFG1), BW always set to 16-bit wide bus
(PEALT)
System Configuration Block
Bootloader Description
164
The bootloader does not perform a checksum of the System
Configuration Block. This means that you can change the
system configuration, by altering the configuration register
settings in the block, to serve as a debugging aid or to en-
able you to use different components (faster or slower
memory).
B.2.2
The KBC Header includes the following code dependent in-
formation: size, checksum and pointers to various KBC rou-
tines. Typically, it is located immediately before the KBC
BIOS, but it may exist anywhere in External Memory. The
KBC Header definitions are:
A valid header has a code size that is non-zero and non-
FFh to protect against a block of zero bytes passing check-
sum. The code size has a granularity of 256 bytes allowing
a maximum size of 64K bytes (actual code size is limited to
56K bytes). Pointers to code stored in the header are code
labels generated by the compiler and assembler. To calcu-
late the actual physical address from the code label, simply
shift the code label one bit to the left to obtain the physical
address. To ensure that the checksum tests all the BIOS, be
sure that the KBC Header is at the lowest physical address
(preferably, immediately after the System Configuration
Block). The OEM_Detect_Crisis routine is intended to per-
form more extensive testing on the BIOS Flash than possi-
ble in a simple bootloader program. It can, however, be
used for other initialization and system configuration pur-
poses by strap pins.
Note:
B.3
In developing the bootloader, every effort has been made to
minimize the resources it uses and maximize the PC87570
features available to the user.
B.3.1
GPIO pins are used as an External Memory memory bus
width configuration strap and to indicate Flash memory fail-
ure. The definitions are shown in the following table.
0 Signature byte set to 33h
1 Signature byte set to CCh
2 KBC BIOS size (not including this header)
3 Byte to force checksum = 0 (checksum is done on
4 Pointer to user-defined OEM_Detect_Crisis rou-
6 Pointer to KBC BIOS entry point
KBC code and header, not System Configuration
Block)
tine/label within BIOS code (code label, not abso-
lute address, where FFFFh signifies that this
routine/label is not implemented)
SYSTEM RESOURCES USED BY BOOTLOADER
KBC Header
GPIO Pins
Zero all unused memory included in the checksum
area to avoid checksum errors.