ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 73

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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6.6.1
Bits 4-0 - Reserved
Bit 5 - Software Off Command (SOC)
Bit 6 - Reserved
Bit 7 - Power Off (PF)
6.6.2
Bit 0 - Time Match Enable (TME)
Bit 1 - Reserved
Bit 2 - RING Pulse or Train Detection Mode (RPTDM)
Bit 3 - RING Enable (RE)
Bits 7-4 - Reserved
6.6.3
The bits in this register that detect events are cleared to 0
when this register is read.
Bit 0 - Timer Match Detect (TMD)
Bit 1 - RING Detect (RID)
7
This bit is write-only and non-sticky. Read returns 0.
0: Ignored
1: APC-OFF interrupt signal generated
This bit is set to 1 when RTC/APC switches from V
V
bit has no effect.
0: Pre-determined date or time event ignored
1: APC-ON interrupt generated on a match between
0: RING pulse falling edge detected
1: RING pulse train > 16 Hz for 0.19 s
0: RING input signal ignored
1: APC-ON interrupt generated on RING detection
This bit is set to 1 when the RTC reaches the pre-deter-
mined date, regardless of the value of the TME bit (bit 0
of APCR2).
This bit is set to 1 when a RING pulse or RING pulse
train is detected on the RING input pin, regardless of the
value of the RE bit (bit 3 of APCR2).
RS
PF
7
7
BAT
Reserved
the RTC and the pre-determined date or time
APC Control Register 1 (APCR1)
APC Control Register 2 (APCR2)
APC Status Register (APSR)
. Cleared to 0 by writing 1 to this bit. Writing 0 to this
6
Res
6
4
Reserved
SOC
5
RE
3
Real-Time Clock (RTC) and Advanced Power Control (APC)
4
RPTDM
2
2
Reserved
Res
RID
1
1
TME
TMD
0
0
CC
0
to
73
Bits 6-2 - Reserved
Bit 7 - RING Status (RS)
6.6.4
Once a non-reserved bit is set to 1, it can be cleared only by
a hardware (HMR pin) reset.
Bits 2-0 - Reserved
Bit 3 - Upper RAM Block (URB)
Bit 4 - RAM Block Read (RBR)
Bit 5 - RAM Block Write (RBW)
Bit 6 - RAM Mask Write (RMW)
This bit controls writes to all RTC RAM.
Bit 7 - RAM Lock (RL)
Holds the instantaneous value of the RING pin.
Controls access to the upper 128 RAM bytes, accessed
via the Upper RAM Address and Data Ports of Bank 1
0: No effect on upper RAM access
1: Upper RAM Data Port of Bank 1 blocked; writes are
This bit controls reads from Upper RAM bytes 00h-1Fh.
0: No effect on upper RAM access
1: Reads from bytes 00h-1Fh of upper RAM return
This bit controls writes to bytes 00h-1Fh of upper RAM.
0: No effect on upper RAM access
1: Writes to bytes 00h-1Fh of upper RAM ignored
0: No effect on RAM access
1: Writes to bytes 0Eh-3Fh of all banks, bytes 40h-
0: No effect on RAM access
1: Read and write to locations 38h-3Fh of all bank
RL
7
ignored and reads return FFh
FFh
7Fh of Bank 0 and to all upper RAM ignored
blocked; writes ignored and reads return FFh.
RAM Lock Register (RLR)
RMW
6
RBW
5
RBR
4
URB
3
2
Reserved
0