ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 88

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

11.0 General Purpose I/O (GPIO) Ports
The PC87570 provides up to 76 GPIO pins. Some GPIO
signals share their pins with an alternate function (see Sec-
tion 2.5 on page 27).
11.1 FEATURES
The GPIO ports are subdivided into the following groups,
each with its own unique set of features:
Figure 11-1 illustrates a GPIO port diagram which includes
all available features.
Ports PA(0-6), PB(0-7), PC(0-7) and PE(0-1) are on-
chip bidirectional (I/O) ports that support GPIO alter-
nate functions and an internal weak pull-up. The fol-
lowing exceptions apply:
— PA has no PxALT register. Its alternate function is
— PBALT.6 is always 1, i.e., configured for its alternate
— PBDIR.5 and PBDOUT.5 are set on reset, configur-
— Port PC is initialized on power-up and WATCHDOG
Ports PF(0-7), PG(0-4) and PH(0-5) are bidirectional
(I/O) ports that support GPIO alternate functions but
do not have an internal weak pull-up option.
Port PD(0-7) is on-chip input only.
Port KBSIN0-7 is an on-chip input port dedicated to
the keyboard scan with weak pull-up support.
Port KBSOUT0-15 is an on-chip output port dedicated
to the keyboard scan.
Alt Device Data Output
controlled by a strap option.
function.
ing bit 5 to be output with data set. PBALT.5 must al-
ways be set to 0.
reset only. It is unchanged after Warm reset.
Alt Device Data Input
Px = Any GPI port
Alt Device Direction
Data In Register
Data In Read
Weak Pull-up
Alt Function
Data Out
Register
Direction
Register
Register
Register
Signal
{
{
{
{
Figure 11-1. GPIO Port Schematic Diagram
PxDIN
General Purpose I/O (GPIO) Ports
Weak Pull-up
(PxDOUT)
Data Out
(PxWPU)
Direction
PxAlt
(PxDIR)
88
11.2 FUNCTIONAL DESCRIPTION
11.2.1 Output Buffer
The output buffer is a TRI-STATE buffer. The output type
(i.e., CMOS or TTL) and its driving capabilities are de-
scribed in Table 19-7 on page 135.
11.2.2 Input Buffer
The I/O port input buffer characteristics are defined in Table
19-7 on page 135.
The input buffer has an enable input. When enabled, the
buffer inputs the pin’s logic level to the on-chip modules.
When disabled, the input is blocked to prevent supply leak-
age currents.
11.2.3 Open Drain
To use the GPIO pin as an inverting open-drain output buff-
er, the software should clear the corresponding bit in the
Data Out (PxDOUT) register, and then use the direction
register to set the value to the port pin.
11.2.4 Weak Pull-Up
The internal weak pull-up can be used to pull-the signal high
when it is not forced low, by writing (1) to the corresponding
bit of PxWPU. Pull-up characteristics are defined in Table
19-7 on page 135.
Alt
1
When the signal’s direction is set as output (1), a val-
ue of 0 is forced.
When the direction is set for input (0), the signal is in
TRI-STATE and is not forced low.
Alt
Alt
Alt
Pull-up
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