ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 51

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

5.6.2
The CR16A writes to the DBBOUT Register when it needs
to send data to the host. When OBF in the HIKMST Register
is set, it indicates that data is available in DBBOUT. DB-
BOUT should be written by the firmware running on the
CR16A only when this bit is cleared.
The PC87570 supports polling and interrupt communication
schemes with the host. Both keyboard interrupt (IRQ1) and
mouse interrupt (IRQ12) schemes are supported.
The CR16A firmware writes data addressed to the key-
board driver (i.e., generates IRQ1) to the HIKDO Register.
A write to HIKDO stores the data in DBBOUT and sets OBF
in the HIKMST Register. If IRQ1 interrupt is enabled
(OBFKIE in the HICTRL Register is set), this is also sent ac-
cording to the interrupt mode (IRQM and IRQNPOL in the
HIIRQC Register).
The CR16A firmware writes data addressed to the mouse
driver (i.e., generates IRQ12) to the HIMDO Register. A
write to HIMDO stores the data in DBBOUT and sets OBF
in the HIKMST Register. If IRQ12 interrupt is enabled
(OBFMIE in the HICTRL Register is set), this is also sent
according to the interrupt mode (IRQM and IRQNPOL fields
in HIIRQC register).
DBBOUT Register
Interrupts to CR16A
Interrupts to the host
Output
Empty
Buffer
(KBD)
IRQ1
(Mouse)
Buffer
IRQ12
Input
Full
HIKMST
STATUS
STATUS
FEA4h
0064h
Host Bus Interface (HBI)
Figure 5-2. KBC Channel
51
Resident Device Bus
0064h
COMMAND
5.6.3
The data buffer has two latches: one serves as an input
buffer and the other as an output buffer. When writing to ad-
dress 60h or address 64h
ister. HA2 of the host address is latched in the Status
Register to identify which address was written to. When the
host writes to DBBIN, IBF in the Status Register is set.
The CR16A can identify that data is present in the input
buffer by either polling IBF or acknowledging an interrupt
when IBFCIE in the HICTRL Register is enabled.
When the input buffer is identified as full, the Status Regis-
ter should be read (A2 in the HIKMST Register) to deter-
mine which address was written to. The CR16A can then
read the data from the input buffer (the HIKMDI Register).
IBF is cleared when the data input buffer is read by the
CR16A.
The host identifies the presence of data in the output buffer
by either polling the Status Register (reading address 64h)
or by responding to IRQ1 or IRQ12. The host can read data
using a read operation from address 60h. This clears the
OBF in the HIKMST Register. In addition, when the host in-
terrupt is in level mode (IRQM in the HIIRQC Register is 0)
and the hardware interrupt is enabled, IRQ1 or IRQ12 is de-
asserted (low if IRQNPOL in the HIIRQC Register is 0).
The CR16A can read OBF to identify when the output buffer
is empty and ready for new data to be transferred. When the
output buffer full interrupt to the core is enabled (OBECIE in
the HICTRL Register is 1), the interrupt signal to the ICU is
set high if OBF is set to 0.
Peripheral Bus
HIKMDI
DBBIN
FEAAh
DBBIN Register
0060h
DATA
HIKDO
FEA6h
,
DBBOUT
data is written to the DBBIN Reg-
0060h
DATA
HIMDO
FEA8h
D0-7
D0-7
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