ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 38

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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3.3.4
If the BCFG.EWR configuration bit is 0, the BIU uses the
late write bus cycle. The basic late write bus cycle takes two
clock cycles. This write bus cycle requires the RD signal in
the memory device interface.
A write bus cycle starts at T1, when the data bus is in TRI-
STATE, the address is placed on the address bus and SELn
(or SELIO) is activated. Next, WR0-1 are activated; RD is
inactive to indicate this is a write transaction.
At the first TIW or T2 (when there is no TIW cycles), the data
is placed on the data bus. The bus cycle is completed at T2,
when WR0-1 deactivates; the address and data remain val-
id until T2 is completed.
Data placed
on D0-15
Note: Any reference to SZCFGn also applies to the IOCFG Register.
Hold cycles
according to
SZCFGn.HOLD
First T
SELn inactive
TIW
Late Write Bus Cycle
SZCFGn.WAIT
Any reference to SELn also applies to the SELIO signal.
Internal waits completed
hold
Hold cycles completed
SZCFGn.HOLD
Internal waits corresponding to SZCFGn.WAIT
0
T
hold
0
Figure 3-4. Late Write Bus Cycle
Bus Interface Unit (BIU)
begin
end
T2
T1
T1
SZCFGn.HOLD=0
38
After T2, the number of T
Gn.HOLD (may be 0) are added. When T
added, the address and data remain valid until the end of
the last T
first T
(or SELIO) is deactivated in the clock cycle after T2, unless
another read or write from the same zone follows. The data
is put in TRI-STATE in the clock cycle after the last T
T2 (if no T
3-6.
Address placed on A0-15
SELn: activated
WR0-1: activated
Data placed on D0-15
WR0-1: inactive
Address on A0-15 invalid/changed
Data put in TRI-STATE
SELn inactive
hold
hold
cycle. When no T
hold
cycle. SELn (or SELIO) is deactivated on the
cycle is configured). See Figures 3-4, 3-5 and
hold
hold
cycles specified by SZCF-
cycles are specified, SELn
SZCFGn.WAIT = 0
hold
cycles are
hold
or