ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 91

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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12.2.4 Interrupt Signals
The firmware can use an interrupt driven scheme to imple-
ment the PS/2 device interface. When the shift mechanism
is not in use, three interrupts are available: PSINT1,
PSINT2 and PSINT3, one for each channel. When the shift
mechanism is in use, only one interrupt signal is used
(PSINT1). More details on the use of the interrupts are pro-
vided in Section 12.2.5. Figure 12-2 illustrates the interrupt
scheme with the associated enable bits.
12.2.5 Power Modes
The PS/2 interface is active only when the PC87570 is in
Active mode. The shift mechanism should be disabled be-
fore entering Idle mode. In Idle mode, the state of output
signals cannot be changed (i.e., the firmware cannot write
to PSOSIG register and the shift mechanism does not func-
tion).
When the PC87570 must wake up on a Start bit detection
by the MIWU, the PS/2 channels that may serve as wake-
up event sources must be enabled before entering Idle
mode. To enable them, set their corresponding CLK bits in
the PSOSIG Register.
The MIWU module can be used to identify a start bit in Idle
mode and to turn the PC87570 back to Active mode. The
MIWU receives PSCLK1, PSCLK2, PSCLK3, PSDAT1,
PSDAT2 and PSDAT3 signals as inputs (see Table 2-5 on
page 27). It should be programmed to identify a low level on
the clock or data lines of the enabled channels. In this con-
figuration, a start bit causes the PC87570 to switch from Idle
mode to Active mode. Once Active mode is reached, the
firmware should cancel the transaction just started and then
enable a re-transmission of the information by the device.
PSTAT.SOT
PSTAT.EOT
Input Buffer Data
Output Buffer Data
PSCLK1
PSCLK2
PSCLK3
Figure 12-2. PS/2 Interface Interrupt Signals
PSIEN.DSMIE
PSIEN.EOTIE
PSIEN.SOTIE
Figure 12-3. Quasi Bidirectional Buffer
Rising Edge
Detector
PSINT1
PSINT2
PSINT3
PS/2 Interface
91
12.3 SHIFT MECHANISM ENABLED
Figure 12-4 illustrates the shift mechanism PS/2 data
transfer sequence detailed in this section.
12.3.1 Reset
Clearing the shift mechanism enable bit (PSCON.EN = 0),
or all the channels’ clock bits (CLK1, CLK2 and CLK3 = 0)
resets the shift mechanism. In this state, the PSTAT register
is cleared (00h), and the state of the PS/2 clock and data
signals (PSCLK1, PSCLK2, PSCLK3, PSDAT1, PSDAT2
and PSDAT3) is set according to the value of their control
bits (CLK1, CLK2, CLK3, WDAT1, WDAT2 and WDAT3, re-
spectively).
When the shift mechanism is reset while in an unknown
state or while in Transmit Idle state, the firmware should set
(1) WDAT1, WDAT2 and WDAT3 before the shift mecha-
nism is reset.
Before disabling the shift mechanism, the software should
clear (0) CLK1, CLK2 and CLK3, to prevent glitches on the
clock signals.
12.3.2 Enable
To enable the shift mechanism, verify that PSOSIG is set to
07h and then set (1) PSCON.EN bit. This puts the shift reg-
ister state machine in Receive Inactive or Transmit Inactive
states (PSCON.XMT is 0 or 1 respectively). In either of
these states, the clock signals (PSCLK1, PSCLK2 and
PSCLK3) are low and the data signals PSDAT1, PSDAT2
and PSDAT3 are either floating or pulled high.
12.3.3 General PS/2 Interface Operation
Shift Status
The PSTAT register indicates the current status of the shift
mechanism. The data transfer process may be in one of the
following three states:
Shifter Empty: The shift mechanism is in either Receive
Inactive, Receive Idle, Transmit Inactive or Transmit Idle
states. The PSTAT is cleared because none of the enabled
devices has sent a start bit.
PSCON.WPUEN
Q1
Q2
+V
Q3
CC