ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 62

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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coding the RTC module address. Data written to this bit is
ignored. On reset, this register is initialized to 70h. It may be
updated if RTCLK in the FLR Register is 0.
The HRTCCS is an internal, chip select signal that identifies
access to the RTC module. (In some cases, the RTC’s leg-
acy address is used instead.) This signal is active (0) when
the accessed address is the address held in RTCCSAH and
RTCCSAL, or the consecutive address (i.e., address line
A0 is ignored in the decoding), if RTCE in the FER Register
is 1.
On reset, the RTC is mapped to its legacy address 0070h
and 0071h. The HDEN strap input defines if, on reset, access
to the RTC is enabled (HDEN=1) or disabled (HDEN=0).
5.14.8
The KBCCSAH Register holds the high address bits of the
KBC interface channel (legacy ports 0060h and 0064h).
Bits 0 through 7 of this register hold the host bus address
bits 8 through 15, respectively. On reset, this register is ini-
tialized to 00h. It may be updated if KBCLK in the FLR Reg-
ister is 0.
5.14.9
The KBCCSAL Register holds the low address bits of the
KBC interface channel (legacy ports 0060h and 0064h).
Bits 0 through 7 of this register hold the host bus address
bits 0 through 7, respectively. Bit 2 is a read only bit, and
holds the value 0. This bit is ignored when decoding the
KBC channel address. Data written to this bit is ignored. On
reset, this register is initialized to 60h. It may be updated if
KBCLK in the FLR Register is 0.
HKBCCS is an internal, chip select signal that identifies an
access to the KBC interface channel. (In some cases, the
channel legacy address is used instead.) This signal is ac-
tive (0) when the accessed address is the address held in
KBCCSAH and KBCCSAL, or that address + 4 (i.e., ad-
dress line A2 is ignored), if KBCE in the FER Register is 1.
On reset, the KBC interface channel is mapped to its legacy
address 0060h and 0064h. The HDEN strap input defines if,
on reset, access to the KBC interface channel is enabled
(HDEN=1) or disabled (HDEN=0).
5.14.10 PM Chip Select Address High Register (PMCSAH)
The PMCSAH Register holds the high address bits of the
host interface PM channel (legacy ports 0062h and 0066h).
Bits 0 through 7 of this register hold the host bus address
7
7
7
KBC Chip Select Address High Register (KBCCSAH)
KBC Chip Select Address Low Register (KBCCSAL)
6
6
6
5
5
5
Address High HA15-8
Address Low HA7-0
Address Low HA7-0
4
4
4
3
3
3
2
2
2
1
1
1
Host Bus Interface (HBI)
0
0
0
62
bits 8 through 15, respectively. On reset, this register is ini-
tialized to 00h. It may be updated if PMLK in the FLR Reg-
ister is 0.
5.14.11 PM Chip Select Address Low Register (PMCSAL)
The PMCSAL Register holds the low address bits of the
host interface PM channel (legacy ports 0062h and 0066h).
Bits 0 through 7 of this register hold the host bus address
bits 0 through 7, respectively. Bit 2 is a read only bit and
holds the value 0. This bit is ignored when decoding the PM
channel address. Data written to this bit is ignored. On re-
set, this register is initialized to 62h. It may be updated if
PMLK in the FLR Register is 0.
The PMCSA Register, together with the PMCSAH Register,
define the address used when accessing the PM channel of
the host interface. HPMCS is an internal, chip select signal
that identifies an access to the PM channel. (In some cases
the channel legacy address is used instead.) This signal is
active (0) when the accessed address is the address held in
PMCSAH and PMCSAL, or that address + 4 (i.e., address
line A2 is ignored) if PME in the FER Register is 1.
On reset, the PM channel is mapped to its legacy address
0062h and 0066h. The HDEN strap input defines if, on re-
set, access to the PM channel. is enabled (HDEN=1) or dis-
abled (HDEN=0).
5.14.12 Function Enable Register (FER)
The FER Register enables and disables the host interface to
various functions in the PC87570. On reset, the host may
change the contents of the bits in this register. Bits in FER may
be write protected (locked) by setting the corresponding bit in
the FLR Register. The HDEN strap input is sampled during
power-up reset. FER is initialized on reset according to HDEN.
When HDEN=0, FER is initialized to 00, disabling all modules.
When HDEN=1, non-reserved bits of FER are set, enabling
access to the devices at their default addresses.
Bit 0 - RTC Enable (RTCE)
Bit 1 - KBC Enable (KBCE)
7
7
7
0: RTC cannot be accessed by the host; i.e., access
1: A read or write access by the host to the address
0: Keyboard channel cannot be accessed by the host; i.e.,
to the address specified in RTCCSAH, RTCCSAL
does not generate a chip select.
specified by RTCCSAH, RTCCSAL generates a
chip select to the RTC (HRTCCS).
access to the address specified in KBCCSAH,
KBCCSAL does not generate a chip select.
6
6
6
Reserved
5
5
5
Address High HA15-8
Address Low HA7-0
4
4
4
3
3
3
PME KBCE RTCE
2
2
2
1
1
1
0
0
0