ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 77

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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7.2.2
The HFCG maintains an internal 14-bit HFCGI variable.
The HFCGI variable is defined by two byte-wide registers:
HFCGIL and HFCGIH. If new HFCGM and HFCGN values
are loaded, the frequency multiplier automatically searches
for the HFCGI value needed to lock onto the target frequen-
cy. The locking process can take up to several milliseconds
to complete. The HFCGI variable can be recorded for a giv-
en HFCGM and HFCGN set of values and used later to re-
duce the time needed for frequency locking.
To record the HFCGI value:
1. Read the HFCGIL value.
2. Check if the IVLID bit in the HFCGCTRL Register is set
3. Read the HFCGIH value.
To fast load a new setting, load the HFCGM and HFCGN
values, and the corresponding HFCGI value. Then set the
FAST bit in the HFCGCTRL Register to 1; the frequency
multiplier quickly locks onto the target frequency without
searching for a new HFCGI value.
To fast set a new clock frequency:
1. Write the HFCGN value.
2. Write the HFCGML value.
3. Write the HFCGMH value.
4. Write the HFCGIL value.
5. Write the HFCGIH value.
6. Set the FAST bit in the HFCGCTRL Register to 1.
Changes in temperature or voltage may cause variations in
the value of HFCGI for a given output frequency. If these
changes occur in the interval between recording the HFCGI
to its use, the output frequency generated following a fast
frequency setting may differ from the target frequency.
However, after some time, the output frequency converges
to the desired frequency.
7.3 HFCG REGISTERS
7.3.1
The HFCGCTRL Register is a byte-wide, read/write register
that sets the frequency multiplier’s operating parameters.
Upon power-up and WATCHDOG reset, bits 0 through 3
are initialized to Ch.
Bit 0 - Load M and N Values (LOAD)
Bit 1 - Load M, N and I Values (FAST)
7
Res
to 0. If yes, repeat stages 1 and 2.
Write 1 to the LOAD bit to perform a normal frequency
change by loading the HFCGML, HFCGMH and
HFCGN buffer data to the frequency multiplier. The bit
always reads back as 0. LOAD must be cleared (0)
when FAST bit is set.
Write 1 to the FAST bit to perform a fast frequency
change by loading the HFCGML, HFCGMH, HFCGN,
HFCGIH and HFCGIL input buffer data in the frequency
multiplier. The bit always reads back 0. FAST must be
cleared (0) when LOAD is set.
5
Fast Clock Setting
HFCG Control Register (HFCGCTRL)
IVLID
4
OHFC
3
ENABLE
2
High Frequency Clock Generator (HFCG)
FAST
1
LOAD
0
77
Bit 2 - Multiplier Enable (ENABLE)
ENABLE is a read only bit. It provides the status of the PMC
Bit 3 - Output Clock Status (OHFC)
Bit 4 - I Value Valid (IVLID)
7.3.2
The HFCGML Register is a byte-wide, read/write register
containing the lower eight bits of the frequency multiplier
HFCGM value. Data written to the register is stored in the
setup buffer. Reading the register returnees the current sta-
tus of the frequency set registers. Upon power-up and
WATCHDOG reset it is loaded with C5h.
7.3.3
The HFCGMH Register is a byte-wide, read/write register
containing the upper six bits of the frequency multiplier
HFCGM value. Data written to the register is stored in the
setup buffer. Reading the register returns the current status
of the frequency set registers. Upon power-up and WATCH-
DOG reset, it is loaded with 04h.
7.3.4
The HFCGN Register is a byte-wide, read/write register con-
taining five bits of the frequency multiplier HFCGN value. Data
written to the register is stored in the setup buffer. Reading the
register returns the current status of the frequency set regis-
ters. Upon power-up and WATCHDOG reset, it is loaded with
0Ah.
7
7
enable/disable command. Any data written to this bit is
ignored.
0: Disabled
1: Enabled
OHFC is a read only bit. It indicates when the HFCG is
oscillating and produces a stable clock. Any data written
to this bit is ignored.
0: Not oscillating
1: Oscillating with stable output
IVLID is a read only bit; data written to it is ignored. This
bit has meaning only after the first read from the
HFCGIL Register.
0: Data read is invalid; repeat HFCGIL Register read
1: Data read is valid; HFCGIH can be read
7
Res
operation
Res
HFCGM Low Value Register (HFCGML)
HFCGM High Value Register (HFCGMH)
HFCGN Value Register (HFCGN)
6 5
5
4
HFCGM7-0
HFCGM13-8
HFCGN4-0
0
0
0