ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 141

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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Symbol Figure
t
t
t
t
PSCLKia
t
t
t
PSCLKh
PSCLKa
t
t
PSCLKl
CSTOsi
t
t
t
PSDOv
RDYDv
t
t
PSDIh
t
PSDIs
RDYA
OUTv
OUTh
INPh
BUFi
INPs
19-28,
19-28,
19-16 IOCHRDY inactive
19-15 Input setup time PA0-
19-15 Input hold time PA0-
19-14 Output valid time
19-14 Output hold time
19-28 Input setup time
19-28 Input hold time
19-29 Output valid time
19-30 Output active time
19-30 Output inactive time
19-16 HD0-7 valid
19-20 Bus free time
19-20 SCL setup time
19-29
19-29
6, PB0-7, PC0-7,
PD0-7, PE0,1, PF0-7,
PG0-4, PH0-5
6, PB0-7, PC0-7,
PD0-7, PE0-1, PF0-7,
PG0-4, PH0-5
KBSOUT0-15, PA0-
6, PB0-7, PC0-7,
PE0-1, PF0-7, PG0-
4, PH0-5
KBSOUT0-15, PA0-
6, PB0-7, PC0-7,
PE0-1, PF0-7, PG0-
4, PH0-5
PSDAT1-3
PSDAT1-3
PSCLK1-3 low time
PSCLK1-3 high time At 2.0V (both edges)
PSDAT1-3
PSCLK1-3
PSCLK1-3
between Stop and
Start condition
Description
After HIOWR,
HMEMWR, HIORD
or HMEMRD FE
Before RE CLK
After RE CLK
After RE CLK
After RE CLK
Before FE PSCLK1-
3
After RE PSCLK1-3
At 0.8V (both edges) (n + 1)
After FE PSCLK1-3
After RE CLK
After RE CLK
Before IOCHRDY
RE
Before Stop
condition
Conditions
Reference
GPIO Ports Output Signals
ACCESS.bus Input Signals
GPIO Ports Input Signals
Device Specifications
PS/2 Output Signals
PS/2 Input Signals
141
0.5
8
t
(n + 1)
SCLhigho
*
t
t
Min
CLK
SCLri
t
V
*
0
0
0
0
CLK
0
*
CC
t
CLK
t
3
CLK
*
-
= 5 V 10%
3
(n + 6)
0.5
+ 14 ns
30 ns
14 ns
14 ns
Max
*
t
*
CLK
t
CLK
4
(n + 1)
(n + 1)
0.5
8
t
SCLhigho
V
*
t
Min
SCLri
CC
t
*
0
0
0
0
0
CLK
*
*
t
CLK
t
CLK
t
= 3.3 V
CLK
-
3
3
(n + 6)
0.5
+ 14 ns
30 ns
17 ns
17 ns
Max
10%
*
t
*
CLK
t
CLK
4