upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 404

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

404
(4) Synchronization control
Busy control and strobe control are functions used to synchronize transmission/reception between the master
device and a slave device.
By using these functions, a shift in bits being transmitted or received can be detected.
(a) Busy control option
Busy control is a function to keep the serial transmission/reception by the master device waiting while the
busy signal output by a slave device to the master is active.
When using this busy control option, the following conditions must be satisfied.
• Bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1.
• Bit 4 (BUSYE0) of serial status register 0 (CSIS0) is set to 1.
Figure 17-24 shows the system configuration of the master device and slave device when the busy
control option is used.
The master device inputs the busy signal output by the slave device to the BUSY0/BUZ/INTP7/P141 pin.
The master device samples the input busy signal in synchronization with the falling of the serial clock.
Even if the busy signal becomes active while 8-bit data is being transmitted or received,
transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of
the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input
becomes valid. After that, the master transmission/reception is kept waiting while the busy signal is
active.
The active level of the busy signal is set by bit 3 (BUSYLV0) of CSIS0.
BUSYLV0 = 1: Active-high
BUSYLV0 = 0: Active-low
When using the busy control option, select the internal clock as the serial clock. Control with the busy
signal cannot be implemented with the external clock.
Figure 17-25 shows the operation timing when the busy control option is used.
Caution Busy control cannot be used simultaneously with the interval time control function of
Figure 17-24. System Configuration When Busy Control Option Is Used
automatic data transfer interval specification register 0 (ADTI0).
Master device
(78K0/KF1)
CHAPTER 17 SERIAL INTERFACE CSIA0
SCKA0
BUSY0
SOA0
SIA0
User’s Manual U15947EJ3V1UD
SCKA
SIA
SOA
Busy output
Slave device